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M68000 USER’S MANUAL ADDENDUM

MOTOROLA

2.0 SIGNAL DESCRIPTION

Change Figure 3-3 on Page 3-2.

Figure 1. Input and Output Signals (MC68EC000 and MC68SEC000)

2.1 Data Bus (D15-D0)

In Section 3.2 on page 3-4, replace “The MC68EC000 and MC68HC001 use D7-D0 in 8-bit mode, and D15-
D8 are undefined.” with “Using the MC68HC001, MC68EC000, and MC68SEC000 mode pin, you can
statically select either 8- or 16-bit modes for data transfer. The MC68EC000, MC68SEC000, and
MC68HC001 use D7-D0 in 8-bit mode. D15-D8 are undefined.”

2.2 Bus Arbitration Control

In Section 3.4 on page 3-5, the sentence “In the 48-pin version of the MC68008 and MC68EC000, no pin is
available for the bus grant acknowledge signal; this microprocessor uses a two-wire bus arbitration
scheme.” should read “In the 64-pin MC68EC000 and MC68SEC000, no pin is available for the bus grant
acknowledge signal. These microprocessors use a two-wire bus arbitration scheme.”

2.3 System Control

The Mode subsection heading of Section 3.6 on page 3-7 should read ‘‘Mode (MODE) (MC68HC001/
68EC000/68SEC000).’’

2.4 MC68SEC000 Low-Power Mode

Add the following to Sections 4 and 5, Bus Operation.

The MC68SEC000 has been redesigned to provide fully static- and low-power operation. This section
describes the recommended method for placing the MC68SEC000 into a low-power mode to reduce the

ADDRESS BUS

DATA BUS

ASYNCHRONOUS
BUS CONTROL

BUS ARBITRATION
CONTROL

INTERRUPT
CONTROL

PROCESSOR
STATUS

A23-A0

D15-D0

AS

R/W

UDS

LDS

DTACK

BERR

RESET

HALT

MODE

SYSTEM
CONTROL

V

CC

GND

CLK

MC68SEC000

FC0

FC1
FC2

IPL0

IPL1

IPL2

AVEC

BR

BG

F

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Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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Summary of Contents for MC68EC000

Page 1: ...ramming information for the MC68HC000 the MC68HC001 the MC68EC000 and the MC68SEC000 For ease of reading the name M68000 MPUs will be used when referring to all processors Refer to M68000PM AD M68000 Programmer s Reference Manual for detailed information on the MC68000 instruction set The four microprocessors are very similar to each other and all contain the following features Sixteen 32 Bit Data...

Page 2: ... compatible with the MC68010 and the MC68020 32 bit implementation of the architecture 1 1 MC68HC001 The MC68HC001 provides a functional extension to the MC68HC000 HCMOS 16 32 bit microprocessor with the addition of statically selectable 8 or 16 bit data bus operation The MC68HC001 is object code compatible with the MC68HC000 You can migrate code written for the MC68HC001 without modification to a...

Page 3: ...on are combined in the MC68SEC000 for low power applications such as portable measuring equipment electronic games and battery operated hand held consumer products The HCMOS MC68SEC000 s static architecture is a direct replacement for the MC68EC000 which offers the lowest cost entry point to 32 bit processing The internal 32 bit architecture provides fast and efficient processing that satisfies th...

Page 4: ...scheme should read In the 64 pin MC68EC000 and MC68SEC000 no pin is available for the bus grant acknowledge signal These microprocessors use a two wire bus arbitration scheme 2 3 System Control The Mode subsection heading of Section 3 6 on page 3 7 should read Mode MODE MC68HC001 68EC000 68SEC000 2 4 MC68SEC000 Low Power Mode Add the following to Sections 4 and 5 Bus Operation The MC68SEC000 has b...

Page 5: ...output the processor is writing to the low power address in supervisor mode and user designed circuitry should assert the ADDRESS_MATCH signal shown in Figure 2 and Figure 3 Figure 3 MC68SEC000 Low Power Circuitry for 8 Bit Data Bus 2 Execute the STOP instruction The external circuitry shown in Figure 2 and Figure 3 will count the number of bus cycles starting with the write to the low power addre...

Page 6: ...ee state capability to be placed into a high impedance state To place the MC68SEC000 into a three state condition the proper method for arbitrating the bus as described in 5 2 Bus Arbitration in the M68000 User s Manual Rev 8 should be completed during the fetch of the status register data for the STOP instruction A timing diagram with the bus arbitration sequence is shown in Figure 5 Figure 5 MC6...

Page 7: ...ing edge of the system clock Figure 6 shows the timing for bringing the processor out of the low power mode Both the RESTART and RESET signals are subject to the asynchronous setup time as specified in the Electrical Characteristics section of this addendum WARNING The system clock must be stable before the RESTART signal is asserted to prevent glitches in the clock An unstable clock can cause unp...

Page 8: ... 3 0 MC68SEC000 ELECTRICAL SPECIFICATIONS Add to the following table to Section 10 1 3 1 MC68SEC000 MAXIMUM RATINGS 3 2 CMOS CONSIDERATIONS The following change should be made to Section 10 4 CMOS Considerations Although the MC68HC000 and MC68EC000 is implemented with input protection diodes care should be exercised to ensure that the maximum input voltage specification is not exceeded should read...

Page 9: ...elative to the rising edge of the clock 2 This output timing is applicable to all parameters specified relative to the falling edge of the clock 3 This input timing is applicable to all parameters specified relative to the rising edge of the clock 4 This input timing is applicable to all parameters specified relative to the falling edge of the clock 5 This timing is applicable to all parameters sp...

Page 10: ...IL GND 0 8 GND 0 5 0 8 V Input Leakage Current BERR BR DTACK CLK I PL2 IPL0 AVEC MODE HALT RESET Iin 2 5 20 2 5 20 uA Three State Off State Input Current ITSI 2 5 2 5 uA Output High Voltage VOH 2 4 VCC 0 75 V Output Low Voltage IOL 1 6 mA HALT IOL 3 2 mA A23 A0 BG FC2 FC0 IOL 5 0 mA RESET IOL 5 3 mA AS D15 D0 LDS R W UDS VOL 0 5 0 5 0 5 0 5 0 5 0 5 0 5 0 5 V Current Dissipation f 0 Hz ID 0 7 1 0 m...

Page 11: ... 20 0 MHz 1 Cycle time tcyc 100 60 50 ns 2 3 Clock Pulse Width tCL tCH 45 45 27 27 21 21 ns 4 5 Clock Rise and Fall Times tCr tCf 10 10 5 5 4 4 ns 0 8 V 2 0 V 4 5 1 2 3 NOTE Timing measurements are referenced to and from a low voltage of 0 8 V and a high voltage of 2 0 V unless otherwise noted The voltage swing through this range should start outside and pass through the range such that the rise o...

Page 12: ...15 15 10 ns 142 AS and LDS UDS Read Width Asserted 195 120 100 ns 14A2 LDS UDS Width Asserted Write 95 60 50 ns 152 AS LDS UDS Width Negated 105 60 50 ns 16 Clock High to Control Bus High Impedance 55 50 42 ns 172 AS LDS UDS Negated to R W Invalid 15 15 10 ns 181 Clock High to R W High Read 0 35 0 30 0 25 ns 201 Clock High to R W Low Write 0 35 0 30 0 25 ns 20A2 6 AS Asserted to R W Low Write 10 1...

Page 13: ... is exceeded BG may be reasserted NUM CHARACTERISTIC 10MHz 16MHz 20MHz UNIT MIN MAX MIN MAX MIN MAX 29 AS LDS UDS Negated to Data In Invalid Hold Time on Read 0 0 0 ns 29A AS LDS UDS Negated to Data In High Impedance Read 150 90 75 ns 30 AS LDS UDS Negated to BERR Negated 0 0 0 ns 312 5 DTACK Asserted to Data In Valid Setup Time on Read 65 50 42 ns 32 HALT and RESET Input Transition Time 0 150 0 1...

Page 14: ...C 47 guarantees their recognition at the next falling edge of the clock 2 BR need fall at this time only to insure being recognized at the end of the bus cycle 3 Timing measurements are referenced to and from a low voltage of 0 8 V and a high voltage of 2 0 V unless otherwise noted The voltage swing through this range should start outside and pass through the range such that the rise or fall is li...

Page 15: ... Timing measurements are referenced to and from a low voltage of 0 8 V and a high voltage of 2 0 V unless otherwise noted The voltage swing through this range should start outside and pass through the range such that the rise or fall is linear between 0 8 V and 2 0 V 2 Because of loading variations R W may be valid after AS even though both are initiated by the rising edge of S2 specification 20A ...

Page 16: ...imum 55 50 42 ns 16 Clock High to Control Bus High Impedance 55 50 42 ns 33 Clock High to BG Asserted 0 35 0 30 0 25 ns 34 Clock High to BG Negated 0 35 0 30 0 25 ns 35 BR Asserted to BG Asserted 1 5 3 5 1 5 3 5 1 5 3 5 Clks 36 BR Negated to BG Negated 1 5 3 5 1 5 3 5 1 5 3 5 Clks 38 BG Asserted to Control Address Data Bus High Impedance AS Negated 55 50 42 ns 39 BG Width Negated 1 5 1 5 1 5 Clks ...

Page 17: ...DTACK IPL2 IPL0 and VPA guarantees their recognition at the next falling edge of the clock BR BG AND R W STROBES CLK 33 35 BR BG AS DS R W FC2 FC0 A19 A0 D7 D0 47 38 36 58 NOTE Waveform measurements for all inputs and outputs are specified at logic high 2 0 V logic low 0 8 V 34 58A 39 A23 D15 LDS UDS Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to w...

Page 18: ...R BG AS DS VMA R W FC2 FC0 A23 A0 D15 D0 NOTES Waveform measurements for all inputs and outputs are specified at logic high 2 0 V logic low 0 8 V This diagram also applies to the 68EC000 33 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 19: ...16 BR BG AS DS VMA R W FC2 FC0 A23 A0 D15 D0 NOTE Waveform measurements for all inputs and outputs are specified at logic high 2 0 V logic low 0 8 V This diagram also applies to the 68EC000 7 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 20: ...DS VMA R W FC2 FC0 A23 A0 D15 D0 47 39 39 38 36 58 NOTES Waveform measurements for all inputs and outputs are specified at logic high 2 0 V logic low 0 8 V This diagram also applies to the 68EC000 Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc ...

Page 21: ...tible with the MC68EC000 Figure 16 64 Lead Quad Flat Pack and 64 Lead Thin Quad Flat Pack R W 64 17 32 33 16 1 48 49 DTACK BG BR VCC VCC CLK GND MODE HALT RESET AVEC BERR IPL2 IPL1 IPL0 FC2 D12 D13 D14 D15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 D4 LDS UDS AS D0 D1 D2 D3 GND D5 D6 D7 D8 D9 D10 D11 A4 FC1 FC0 A0 A1 A2 A3 GND A5 A6 A7 A8 A9 A10 A11 A12 MC68SEC000FU PB Freescale Semiconductor I F...

Page 22: ...6 95 17 45 0 667 0 687 B 13 90 14 10 0 547 0 555 C 16 95 17 45 0 667 0 687 D 13 90 14 10 0 547 0 555 G 0 30 0 45 0 012 0 018 H 0 80 BSC 0 031 BSC K 2 15 2 45 0 085 0 096 L 0 13 0 23 0 005 0 009 M 2 00 2 40 0 79 0 094 R 12 00 REF 0 472 REF S 12 00 REF 0 472 REF G R D C H M K L B S A Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freescale com nc...

Page 23: ...SC A1 6 00 BSC 0 236 BSC B 10 00 BSC 0 394 BSC B1 5 00 BSC 0 197 BSC C 12 00 BSC 0 472 BSC C1 6 00 BSC 0 236 BSC D 10 00 BSC 0 394 BSC D1 5 00 BSC 0 197 BSC G 0 17 0 27 0 007 0 011 H 0 50 BSC 0 020 BSC K 1 60 0 063 L 0 09 0 20 0 004 0 008 M 1 35 1 45 0 053 0 057 G D D1 C1 C H M K L B B1 A1 A Freescale Semiconductor I Freescale Semiconductor Inc For More Information On This Product Go to www freesc...

Page 24: ...IP Plastic Quad Pack PLCC Plastic Quad Gull Wing Pin Grid Array Solder Lead Finish Pin Grid Array Gold Lead Finish 8 10 12 16 20 MHz 3 8 10 12 16 20 MHz 3 8 10 12 16 20 MHz 3 8 10 12 16 20 MHz 3 Plastic Quad Pack PLCC 8 10 12 16 20 MHz 3 MC68HC001 PACKAGE FREQUENCY VOLTAGE 5V Plastic Quad Pack PLCC Plastic Quad Gull Wing Pin Grid Array Gold Lead Finish 8 10 12 16 MHz 8 10 12 16 MHz 8 10 12 16 MHz ...

Page 25: ...o 85C MC68HC000 Ordering Information PACKAGE BODY SIZE LEAD SPACING SPEED INMHZ VOLTAGE SUFFIX TEMPERATURE RANGE DIP 81 91mm X 20 57mm 2 54mm 8 10 12 16 5 0V P 0C to 70C PLCC 25 57mm X 25 27mm 1 27mm 8 10 12 16 20 FN 0C to 70C 8 10 12 16 CFN 40C to 85C MC68EC000 Ordering Information PACKAGE BODY SIZE LEAD SPACING SPEED INMHZ VOLTAGE SUFFIX TEMPERATURE RANGE PLCC 25 57mm X 25 27mm 1 27mm 8 10 12 16...

Page 26: ...failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out...

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