MOTOROLA
MC68341 USER’S MANUAL ADDENDUM
12
43. Additional Note on Cycle Steal
For the external cycle steal mode description on page 6-6, the initial DREQx assertion does not have to be
held off until after the channel is started. If DREQx is already asserted when the channel is started by setting
the channel start bit, an internal DREQx assertion is generated, providing the edge needed for the DMA cycle
to start.
44. DREQx Negation on Burst
On page 6-8, Figure 6-5, and on page 6-10, Figure 6-7, DREQx should negate before the falling edge of S2
(one clock earlier than shown) to prevent another DMA transfer from occurring. See the note above for page
6-5 on Burst Transfer DREQx Negation.
45. DREQ Assert Time
On page 6-21, Figure 6-13: The second DREQx assertion should be shown held for an additional clock to guar-
antee recognition on 2 consecutive clock falling edges. The figure shows it as just being 1 clock period. Note
1 should be deleted.
46. Fast Termination and Burst Request Mode
On the last paragraph of page 6-21, delete the reference to Figure 6-14. Figure 6-14 on page 6-22 is labeled
incorrectly - it actually shows operation with fast termination, cycle steal, and dual address transfers. Also, the
second DREQx signal should be held for 2 consecutive falling edges - the figure shows it being held for only
1 clock edge. Note 1 of Figure 6-14 should be deleted.
47. Typo in DAPI
On page 6-26, for DAPI = 1, the DAR is incremented according to the destination size (not the source size).
48. Additional note on DMA limited rate operation
On page 6-27, in the BB-Bus Bandwidth Field: The DMA “active” count increments only when the DMA channel
is the bus master (each channel has its own counter). If a higher priority bus master forces the channel to
relinquish the bus before completion of the active count, the counter stops until the channel regains the bus.
Higher priority requests could come from 1) the other DMA channel (if it has a higher MAID level), 2) the
CPU32 core (if either the interrupt mask level in the SR or the interrupt request level is higher than the DMA
channel's ISM level), or 3) an external bus request. When the active count is exhausted, the DMA channel
releases the bus, and the “idle” count increments regardless of bus activity.
49. Configuration Error
The Configuration Error description paragraph at the top of page 6-29 should be replaced with “A configuration
error results when 1) either the SAR or DAR contains an address that does not match the port size specified
in the CCR, or 2) the BTC register does not match the larger port size or is zero.”
50. Additional Note on DMA Interrupt Prioritization
Add to the Interrupt Register description on page 6-31: When both DMA channels are programmed to the same
interrupt level, channel 1 is higher priority than channel 2.
