Motorola MC6805R Series Advance Information Download Page 44

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Summary of Contents for MC6805R Series

Page 1: ...rmation MC68 7 05R U SERIES 8 BIT MICROCOMPUTERS JANUARY 1984 This document contains information on a new product Specifications and Information herein are subject to change without notice MOTOROLA INC 1984 ADI 977 ...

Page 2: ...ucts herein to improve reliability function or design Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others ...

Page 3: ...igurations 3 1 MC6805U2 Memory Map 3 1 3 2 MC6805R2 Memory Map 3 2 3 3 MC6805U3 Memory Map 3 3 3 4 MC6805R3 Memory Map 3 4 3 5 MC68705U3 and MC68705U5 Memory Map 3 5 3 6 MC68705R3 and MC68705R5 Memory Map 3 6 3 7 Shared Stack Area 3 7 3 8 Central Processing Unit 3 7 4 1 4 2 4 3 4 4 4 5 4 5 1 4 5 2 4 5 3 4 5 4 4 5 5 Section 4 Programmable Registers Accumulator A Index Register X Program Counter PC ...

Page 4: ...f Check q 1 RAM Self Check Subroutine 6 1 6 2 ROM Checksum Subroutine 6 1 6 3 Analog to Digital Converter Self Check 6 1 6 4 Timer Self Check Subroutine 6 3 Section 7 Reset Clock and Interrupt Structure 7 1 Reset 7 1 7 1 1 Power OnReset POR 7 1 7 1 2 External Reset Input 7 2 7 1 3 Low Voltage Inhibit LVI 7 2 7 2 Internal Clock Generator Options 7 2 7 3 Interrupts 7 5 Section 8 Input Output Circuit...

Page 5: ...y Write Instructions 10 4 Branch Instructions 10 4 Bit Manipulation Instructions 10 4 Control Instructions 10 4 Alphabetical Listing 10 4 Opcode Map Summary 10 4 Section 11 Electrical Characteristics Maximum Ratings 11 1 Thermal Characteristics 11 1 Power Considerations 11 2 MC6805R2 and MC6805R3 Characteristics 11 3 Electrical Characteristics 11 3 Switching Characteristics 11 4 AID Converter Char...

Page 6: ...11 7 4 Port Electrical Characteristics 11 12 11 8 1 0 Characteristics 11 12 Section 12 Ordering Information 12 1 MC6805R2 12 1 12 2 MC6805R3 12 1 12 3 MC6805U2 12 1 12 4 MC6805U3 12 2 12 5 MC68705R3 12 2 12 6 MC68705R5 12 2 12 7 MC68705U3 12 2 12 8 MC68705U5 12 2 12 9 Custom MCUs 12 2 12 9 1 EPROMs 12 2 12 9 2 Verification Media 12 3 12 9 3 ROM Verification Units RVUs 12 3 12 9 4 Flexible Disk 12 ...

Page 7: ...2 MC6805R3 MC6805U3 Timer Block Diagram 5 3 5 3 MC68705R3 MC68705U3 Timer Block Diagram 5 6 5 4 MC68705R5 MC68705U5 Timer Block Diagram 5 7 6 1 Self Check Connections 6 2 7 1 Typical Reset Schmitt Trigger Hysteresis 7 1 7 2 Power and Reset Timing 7 1 7 3 RESET Configuration 7 2 7 4 Clock Generator Options 7 3 7 5 Crystal Motional Arm Parameters and Suggested PC Board Layout 7 4 7 6 Typical Frequen...

Page 8: ...11 5 PortAVOHvslOH 11 13 11 6 PortA VOL vs IOL 11 13 11 7 Port B VOH vs IOH 11 14 11 8 Port B VOL vs IOL 11 14 11 9 PortCVOHvslOH 11 15 11 10 PortCVOLvsIOL 11 15 11 11 Port A Vin vs lin 11 16 11 12 EXTALVin vs lin 11 16 11 13 InterruptVinvslin 11 17 11 14 RESET Vin vs lin 11 17 11 15 VDDvslDD 11 18 11 16 PortsAandCLogicDiagram 11 19 11 17 PortBLogicDiagram 11 19 11 18 Typical Input Protection 11 1...

Page 9: ...on 8 4 10 1 Register Memory Instructions 10 5 10 2 Read Modify Write Instructions 10 6 10 3 Branch Instructions 10 7 10 4 Bit Manipulation Instructions 10 7 10 5 Control Instructions 10 8 10 6 Instruction Set 10 8 10 7 M6805 HMOS Family Instruction Set Opcod Map 10 10 ix x ...

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Page 11: ...puters They are avail able in 40 pin dual in line packages 1 1 DEVICE FEATURES The following tables summarize the hardware and software features of each device Differences between the devices will be highlighted throughout this document when applicable HARDWARE FEATURES MC6805R2 MC6805R3 MC6805U2 MC6805U3 MC68705R3 MC68705U3 MC68705R5 MC68705U5 24 Bidirectional I O Lines X X X X X X X X Eight Inpu...

Page 12: ... Set of Condi tional Branches X X X X X X X X Memory Usable as Registers Flags X X X X X X X X Single Instruction Memory Examine Change X X X X X X X X User Callable Self Check Subroutines X X X X Complete Develop ment System Sup port on EXORciser X X X X X X X X Supported by EPROM Version X X X X 1 2 HARDWARE Every M6805 Family microcomputer contains hardware common to all versions plus a combina...

Page 13: ...ounter PBl 8 Low PCO PCl PC2 Port PC3 C PC4 1 0 PC5 Lines PC6 PCl Figure 1 1 MC6805R2 Block Diagram TIMER PAO PAl Accumulator Port PA2 Data A iN f2 CPU A PA3 Dir Index Control 1 0 PA4 Reg Lines PA5 Register PD X PA6 PDl PA7 Condition PD2 Code PD3 Port D Register CC Input CPU PD4 Lines Stack PD5 PBO Pointer PD6 1NT2 SP PD7 PBl Program Port PB2 B Port Data Counter PB3 B Dir High PCH 1 0 PB4 ALU Line...

Page 14: ...CO PC1 Data Port PC2 Port Dir C PC3 C Reg Reg PC4 1 0 PC5 Lines PC6 PC Figure 1 3 MC6805R3 Block Diagram RESET INT TIMER Accumulator Port Data A CPU INT2 A Dir Index Control 1 0 Reg Register Lines PD X P01 Condition PD2 Code Port D D3 Port D Register CC Input Input CPU PD4 Lines Stack PD5 _ PBO Pointer SP PD6 1NT2 PD PB1 Program Port PB2 Port Data Counter B PB3 B Dir High PCH 1 0 PB4 Reg Reg ALU L...

Page 15: ... ALU PDO ANO PD1 ANl PD2 AN2 PD3 AN3 IH PD4 VRL I i PD5IVRH PD6 rlH I PD7 PCO PCl PC2 POrt PC3 C PC4 1 0 PCS Lines PC6 PCl Figure 1 5 MC68705R3 and MC68705R5 Block Diagram Data Dir Reg Data DII Reo Accumulator Index Register Condition Code Register Stack POinter Program Counter RESET VPP INT A CPU Control X CC CPU PCO PCl SP PC2 PC3 PC4 Port o Input Lines Port D Input Lines Port C I O PC5 High PCH...

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Page 17: ...to these pins to provide a system clock with various degrees of stability cost tradeoffs Lead length and stray capacitance on these two pins should be minimized Refer to SECTION 7 RESET CLOCK AND INTERRUPT STRUCTURE for recommendations about these inputs 2 4 TIMER This pin is used as an external input to control the internal timer counter circuitry On the MC68705R3 MC68705U3 MC68705R5 and MC68705U...

Page 18: ...uts under software control of the data direction registers For the MC6805U2 MC6805U3 MC68705U3 and MC68705U5 port D is for digital input only and bit 6 may be used for a second interrupt fJ JT2 Refer to SECTION 7 RESET CLOCK AND INTER RUPT STRUCTURE and SECTION 8 INPUT OUTPUT CIRCUITRY AND ANALOG TO DIGITAL CONVERTER for additional information For the MC6805R2 MC6805R3 MC68705R3 and MC68705R5 port...

Page 19: ...00 127 128 255 256 1983 1984 3895 3896 4087 1 0 Ports Timer RAM 128 Bytes Page Zero User ROM 128 Bytes Not Used 1728 Bytes Main User ROM 1912 Bytes Self Check ROM 192 Bytes 4088 4089 Timer Interrupt 4090 4091 4092 I External Interrupt I SWI 4093 4094 I 4095 RESET o 7 6 5 4 3 2 1 0 000 0 Port A Data Register 1 Port B Data Register 07F 2 Port C Data Register 080 3 Port D Data Register 4 PortA DDR OF...

Page 20: ...Short Instructions Interrupt Vectors 7 000 127 128 255 256 1983 1984 3895 3896 4087 4088 4089 4090 I 4091 4092 I 4093 4094 I 4095 o 110 Ports 000 Timer RAM 128 Bytes 07F Page Zero User ROM 128 Bytes OFF 100 Not Used 1728 Bytes 7BF 7CO Main User ROM 1912 Bytes F37 F38 Self Check ROM 192 Bytes FF7 FF8 Timer Interrupt FF9 FFA External Interrupt FFB FFC SWI FFD FFE RESET FFF 765 4 321 0 0 Port A Data ...

Page 21: ...091 4092 4093 4094 4095 I O Ports Timer RAM 128 Bytes Main User ROM 3768 Bytes Self Check ROM 192 Bytes Timer Interrupt External Interrupt SWI RESET 7 654 3 2 1 0 000 0 Port A Data Register 1 Port B Data Register 07F 2 Port C Data Register 080 3 Port D Data Register 4 PortA DDR 5 Port B DDR 6 Port C DDR 7 Not Used 8 Timer Data Register 9 Timer Control Register 10 Miscellaneous Register F37 11 F38 ...

Page 22: ...eck ROM 192 Bytes Timer Interrupt External Interrupt SWI RESET 7 6 5 4 3 2 1 0 000 0 Port A Data Register 1 Port B Data Register 07F 2 Port C Data Register 080 3 Port D Data Register 4 PortA DDR 5 Port B DDR 6 Port C DDR 7 Not Used 8 Timer Data Register 9 Timer Control Register 10 Miscellaneous Register F37 11 Not Used F38 3 Bytes 13 14 AI D Control Register FF7 15 AID Result Register FF8 16 FF9 R...

Page 23: ...o select the secure mode of fered by the MC68705U5 Page Zero I000 Access With Short 127 Instructions 128 255 256 3895 3896 3897 3967 3968 4087 4088 4089 4090 Interrupt 4091 Vectors 4092 4093 4094 4095 7 o 1 0 Ports Timer 000 and RAM 128 Bytes 07F Page Zero 080 User EPROM OFF 128 Bytes 100 User Main EPROM 3640 Bytes F37 F38 Mask Option Register F39 Not Used F7F Bootstrap FOO ROM 120 Bytes FF7 FF8 T...

Page 24: ...ro 080 3 Port D Data Register User EPROM OFF 128 Bytes 4 PortA DDR 100 5 Port B DDR User 6 PortC DDR Main 7 Not Used EPROM 8 Timer Data Register 3640 Bytes 9 Timer Control Regi ter 3895 3896 3897 3967 F37 10 Miscellaneous Register 1 F38 Mask Option Register 11 Program Control Register F39 Not Used Not Used F7F 12 3968 Bootstrap F80 13 Not Used ROM 4087 120 Bytes FF7 14 AI D Control Register 4088 4...

Page 25: ... program counter PCl PCH contents being pushed onto the stack the remain ing CPU registers are not pushed The shared stack area must be used with care when it is used for data storage or temporary work locations to protect it from being overwritten due to stacking from an interrupt or subroutine call I Push n 4 n 3 n 2 n l n 7 1 I 1 I 6 5 1 I 1 1 I 1 4 3 2 I Condition Code Register Accumulator Ind...

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Page 27: ...L Interrupt Mask L Half Carry Figure 4 1 Programming Model The accumulator is a general purpose 8 bit register used to hold operands and results of arithmetic calculations or data manipulations 4 2 INDEX REGISTER X The index register is an 8 bit register used for the indexed addressing mode It contains an 8 bit value that may be added to an 8 or 16 bit immediate value to create an effective addres...

Page 28: ...vidually tested by a program and specific action taken as a result of their state Each bit is explained in the following paragraphs 4 5 1 Half Carry H Set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4 4 5 2 Interrupt I When this bit is set the timer and external interrupts INT and INT2 are masked disabled If an interrupt occurs while this bit is set the inter...

Page 29: ...ents a timer interrupt from being processed The MCU responds to this interrupt by saving the present CPU state on the stack fetching the timer interrupt vector from locations FF8 and FF9 and executing the interrupt routine see SECTION 7 RESET CLOCK AND INTERRUPT STRUC TURE The timer interrupt request bit must be cleared by software The TI MER and INT2 share the same interrupt vector The interrupt ...

Page 30: ...This allows a program to determine the length of time since a timer interrupt has occurred and not disturb the counting process At power up or reset the prescaler and counter are initialized with all logic ones the timer interrupt request bit bit 7 is cleared and the timer interrupt mask bit bit 6 is set S 2 MC680SR3 MC680SU3 TIMER CIRCUITRY The timer circuitry for the MC6805R31 MC6805U3 microcomp...

Page 31: ... operating modes plus a disable mode depending on the value written to the TCR4 and TCR5 control bits Refer to 5 2 5 Timer Control Register TCR for further information 5 2 1 Timer Input Mode 1 If TCR5 and TCR4 are both programmed to a zero the input to the timer is from an internal clock and the external TIMER input is disabled The internal clock mode can be used for periodic interrupt generation ...

Page 32: ...in or the internal clock unaffected by RESET 1 Select external clock source Set to a logic one on external reset power on reset or program control 0 Select internal clock source phase two Cleared under program control TCR4 External enable bit control bit used to enable the external TIMER pin unaffected by RESET 1 Enable external TIMER pin Set on external reset power on reset or program control 0 D...

Page 33: ...e The processor is sensitive to the level of the timer interrupt request line therefore if the interrupt is masked the TIR bit may be cleared by software e g BClR without generating an interrupt The TIR bit must be cleared by the timer interrupt service routine to clear the timer interrupt request The timer interrupt and INT2 share the same interrupt vector The interrupt routine thus must check th...

Page 34: ...Select TIE Timer External Input Enable PSC Prescaler Clear PS2 PS1 PSO Prescaler Select Timer Control Register TCR Mask Option Register Bits ClK Clock Oscillator Type TOPT Timer Mask Programmable Option CLS Timer Clock Source P2 Pl PO Prescaler Option NOTE The TOPT bit in the mask option register selects whether the timer s software programmable via the timer control register or emulates the mask ...

Page 35: ...ter ITCR Mask Option Register Bits ClK Clock Oscillator Type TOPT Timer Mask Programmable Option ClS Timer Clock Source ITIE Timer External Input Enable SNM Secure Non Secure Mode Option P2 P1 PO Prescaler Option NOTES The TOPT bit in the mask option register selects whether the timer is software programmable via the timer control register or emulates the mask programmable parts via the MOR PROM b...

Page 36: ...8705U5 bit b3 has no effect on a write reads as a logic one 5 3 1 Software Controlled Mode The TOPT timer option bit b6 in the mask option register is EPROM programmed to a logic zero to select the software controlled mode which is described first TCR bits b5 b4 b3 b2 b1 and bO give the program direct control of the prescaler and input select options The timer prescaler input frequency fPIN can be...

Page 37: ...he prescaler however for the MC68705R5 MC68705U5 bit b3 is set to a logic one and when read by software always reads as a logic one The MOR controlled mode is designed to exactly emulate the MC6805R2 which has only TIM TIR and PSC in the TCR and has the prescaler options defined as manufacturing mask options 5 3 3 Timer Control Register TCR The configuration of the TCR is determined by the logic l...

Page 38: ...and Internal Clocks 1 a No Clock 1 1 External Clock b3 PSC Prescaler Clear When TOPT a this is a write only bit It reads as a logic zero so the BSET and BCLR on the TCR function correctly Writing a one into PSC generates a pulse which clears the prescaler When TOPT 1 operation remains the same for the MC68705R3 MC68705U3 however for the MC68705R5 MC68705U5 this bit is always read as a logic one an...

Page 39: ...C6805R3 MC6805U3 If any error is detected it returns with the Z bit cleared otherwise the Z bit is set The walking diagnostic pattern method is used on the MC6805R2 U2 The MC6805R3 U3 test causes each byte to count from 0 up to 0 again with a check after each count The RAM test must be called with the stack pointer at 07F When run the test checks every RAM cell except for 07F and 07E which are ass...

Page 40: ...02 22 O l JLF T 20 P04 P03 21 L This connection depends on clock oscillator user selectable mask option Use jumper if the RC mask option is selected For the MC6805R2 MC6805U2 pin 7 is not for user application and must be connected to VSS For the MC6805R3 MC6805U3 pin 7 is not connected LED Meanings PCO PCl PC2 PC3 Remarks l LED ON O LED OFF 1 0 1 a Bad I O 0 0 1 0 Bad Timer 1 1 0 0 Bad RAM 0 1 a 0...

Page 41: ... interrupt mask is not set so the caller must protect from interrupts if necessary The A and X register contents are lost The timer self check routine in the MC6805R2 U2 counts how many times the clock counts in 128 cycles The number of counts should be a power of two since the prescaler is a power of two If not the timer probably is not counting correctly The routine also detects a timer which is...

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Page 43: ... senses a logical zero on the RESET pin Out Of Reset In 1 1 Reset 1 1 0 8 V 2 V 4 V VIRES VIRES Figure 7 1 Typical Reset Schmitt Trigger Hysteresis 7 1 1 Power On Reset POR An internal reset is generated upon powerup that allows the internal clock generator to stabilize A delay of tRHL milliseconds is required before allowing the RESET input to go high Refer to the power and reset timing diagram o...

Page 44: ...rnal reset will be removed once the power supply voltage rises above a recovery level VLVR at which time a normal power on reset occurs 7 2 INTERNAL CLOCK GENERATOR OPTIONS The internal clock generator circuit is designed to require a minimum of external components A crystal a resistor a jumper wire or an external signal may be used to generate a system clock with various stability cost tradeoffs ...

Page 45: ...r crystal frequencies other than 4 MHz the total capacitance on each pin should be scaled as the inverse of the frequency ratio For example with a 2 MHz crystal use approximately 50 pF on EXTAL and approximately 25 pF on XTAL The exact value depends on the Motional Arm parameters of the crystal used Figure 7 4 Clock Generator Options When utilizing the on board oscillator the MCU should remain in ...

Page 46: ...l oscillators Follow ceramic resonator manufacturer s sug gestions for CO C and RS values e NOTE Keep crystal leads and circuit connections as short as possible Figure 7 5 Crystal Motional Arm Parameters and Suggest d PC Board Layout B O 7 0 6 0 g5 0 Q J g 4 0 U o 3 0 5l 2 0 o 0 0 0 10 20 VCC 5 25V TA 25 C 30 40 50 Resistance kOl 60 70 Figure 7 6 Typical Frequency Selection for Resistor RC Oscilla...

Page 47: ...d the interrupt routine is executed Stacking the CPU register setting the I bit and vector fetching require a total of 11 tcyc periods for completion A flowchart of the interrupt sequence is shown in Figure 7 7 The interrupt service routine must end with a return from interrupt RTI instruction which allows the MCU to resume processing of the 1 1 inCC 07F SP O DDRs CLR iNi Logic FF Timer 7F Prescal...

Page 48: ...atched on the falling edge of the input signal The INT2 interrupt has an interrupt request bit bit 7 and a mask bit bit 6 located in the miscellaneous register MRl The INT2 interrupt is inhibited when the mask bit is set The INT2 is always read as a digital input on port D The fI IT2 and timer interrupt request bits if set cause the MCU to process an interrupt when the condition code I bit is clea...

Page 49: ...gic zero state placing the ports in the input mode The port output registers are not initialized on reset and should be initialized by soft ware before changing the DDRs from input to output A read operation on a port programmed as an output will read the contents of the output latch regardless of the logic levels at the output pin due to output loading Refer to Figure 8 1 Internal Connections DDR...

Page 50: ...direction registers The register configuration is provided in Figure 7 6 Figure 8 2 provides some examples of port connec tions CAUTION The corresponding DDRs for ports A B and C are write only registers registers at 004 005 and 006 A read operation on these registers is undefined Since BSET and BClR are read modfiy write in function they cannot be used to set or clear a single DDR bit all unaffec...

Page 51: ...e must be exercised when using read modify write instructions since the data read corresponds to the pin level if the DDR is an input zero and corresponds to the latched output data when the DDR is an output onel 8 2 ANALOG TO DIGITAL CONVERTER The MC6805R2 MC6805R3 MC68705R3 and MC68705R5 microcomputers have an 8 bitanalog to digital AI D converter implemented on the chip using a successive appro...

Page 52: ...ng through a 2 6 kilohm resistor typical Refer to Figure 8 4 The converter operates continuously using 30 machine cycles to complete a conversion of the sampled analog input When the conversion is complete the digitized sample of digital value is placed in the AID result register ARR the conversion complete flag is set the selected input is sampled again and a new conversion is started TheA D is r...

Page 53: ...han a 1 LSB with no offset This implies that ignoring errors the transition point from 00 to 01 occurs at Y2 LSB above VRL Similarly the transition from FE to FF occurs 1Y2 LSB below VRH ideally Refer to Figures 8 5 and 8 6 On release of reset the AID control register ACR is cleared therefore after reset channel zero will be selected and the conversion complete flag will be clear Converter Output ...

Page 54: ...l Analog Input Offset Positive Digital Output Digital Output b Full Scale Error FF 00 K _ _ _ _ _ _ _ _ _ _ Analog Input Full Scale Error e Non Linearity FF 00 Analog Input Non Linearity VRH 1 LSB Figure 8 6 Types of Conversion Errors 8 6 ...

Page 55: ...a logic one for MC6805R2 MC6805U2 emulation If the MOR timer option TOPT bit is a zero the MC6805R3 and MC6805U3 are emulated Here bits b5 b4 b2 b1 and bO set the initial value of their respective TCR bits during reset After initiali zation the TCR is software controllable A description of the MOR bits is as follows r b7 b 6 r b 5 b4 b3 r b 2 b 1 b 0 Mask Option 1 1_c_lK 1 1T_o_p_T LI_c_l_s I_ II_...

Page 56: ...1 0 1 32 1 1 0 64 1 1 1 128 Two examples for programming the mask option register are discussed below Example 1 To emulate an MC6805R2 MC6805U2 to verify your program with an RC oscillator and an event count input for the timer with no prescaling the mask option register would be set to 11110000 To write the mask option register it is simply programmed as any other EPROM byte Example 2 Suppose you...

Page 57: ... EPROM programming 0 clear enable EPROM programming if PIE is low PGE is set during a reset however it has no effect on EPROM circuits if VPON is a logic one b2 VPON Vpp ON VPON is a read only bit and when at a logic zero it indicates that a high voltage is present at the Vpp pin 1 no high voltage on Vpp pin 0 high voltage on Vpp pin VPON being one disconnects PGE and PLE from the rest of the chip...

Page 58: ...EPS The MCM2532 UV EPROM must first be programmed with an exact duplicate of the information that is to be transferred to the MC68705R3 MC68705U3 MC68705R5 or MC68705U5 Non EPROM addresses are ignored by the bootstrap Since the MC68705R3 MC68705U3 MC68705R5 or MC68705U5 and the MCM2532 are to be inserted and removed from the circuit they should be mounted in sockets In addition the precaution belo...

Page 59: ...N2222 25 PBO 29 12 20 CLEAR PB4 28 PB3 COUNT I 12 V 1N4001 PB1 PB2 26 27 II u u u Programmed i 1N4001 Verified TO Ol 4 7 k VCC 5 0 V typical V C 11 111711 470 470 VSS O OV CC Vpp 21 0 V 1 0 V Programming Mode Summary of Programming Steps 1 When plugging in the MC68705R3 MC68705U3 MC68705R5 or MC68705U5 or the MCM2532 be sure that Sl and S2 are closed and that VCC and 26 V are not applied 2 To init...

Page 60: ... MC6805R3 and MC6805U3 use the reserved ROM for the self check feature while the MC68705R3 MC68705U3 MC68705R5 and MC68705U5 use this area for the bootstrap program 3 The MC6805R2 MC6805U2 and MC6805R3 MC6805U3 read all ones in their 48 byte future RAM area This RAM is not implemented in the MC6805R2 MC6805U2 and MC6805R3 MC6805U3 mask ROM version but is implemented in the EPROM version M C68705R3...

Page 61: ...ead modify write functions they cannot be used to set a data direc tion regiser bit all unaffected bits would be set It is recommended that all data direc tion register bits in a port be written using a single store instruction The coding examples shown in Figure 10 1 illustrate the usefulness of the bit manipulation and test instruction Assume that the microcomputer is to communicate with an exte...

Page 62: ... extended addressing modes are capable of referenc ing arguments anywhere in memory with a single three byte instruction When using the Motorola assembler the user need not specify whether an instruction uses direct or extended addressing The assembler automatically selects the shortest form of the instruction 10 2 4 Relative The relative addressing mode is only used in branch instructions In rela...

Page 63: ...ar a single DDR bit all unaffected bits would be setl It is recommended that all DDR bits in a port must be written using a single store instruction 10 2 9 Bit Test and Branch The bit test and branch addressing mode is a combination of direct addressing and relative address ing The bit which is to be tested and condition set or clear is included in the opcode and the address of the byte to be test...

Page 64: ...n the read modify write instructions though it does not perform the write Refer to Table 10 2 10 3 3 Branch Instructions The branch instructions cause a branch from the program when a certain condition is met Refer to Table 10 3 10 3 4 Bit Manipulation Instructions These instructions are used on any bit in the first 256 bytes of memory see Caution under paragraph 10 2 8 One group either sets or cl...

Page 65: ...B 2 5 DB 3 6 0 Add Memory and Carry to A ADC A9 2 2 B9 2 4 C9 3 5 F9 1 4 E9 2 5 D9 3 6 Subtract Memory SUB AO 2 2 BO 2 4 CO 3 5 FO 1 4 EO 2 5 DO 3 6 Subtract Memory from A with Borrow SBC A2 2 2 B2 2 4 C2 3 5 F2 1 4 E2 2 5 D2 3 6 AND Memory to A AND A4 2 2 B4 2 4 C4 3 5 F4 1 4 E4 2 5 D4 3 6 OR Memory with A ORA AA 2 2 BA 2 4 CA 3 5 FA 1 4 EA 2 5 DA 3 6 Exclusive OR Memory with A EOR AS 2 2 BS 2 4 ...

Page 66: ...A 1 6 6A 2 7 Clear CLR 4F 1 4 5F 1 4 3F 2 6 7F 1 6 6F 2 7 Complement COM 43 1 4 53 1 4 33 2 6 73 1 6 63 2 7 Negate 2 8 Complement NEG 40 1 4 50 1 4 30 2 6 70 1 6 60 2 7 Rotate Left Thru Carry ROL 49 1 4 59 1 4 39 2 6 79 1 6 69 2 7 Rotate Right Thru Carry ROR 46 1 4 56 1 4 36 2 6 76 1 6 66 2 7 Logical Shift Left LSL 48 1 4 58 1 4 38 2 6 78 1 6 68 2 7 Logical Shift Right LSR 44 1 4 54 1 4 34 2 6 74 ...

Page 67: ...4 Branch IFF Half Carry Set BHCS 29 2 4 Branch IFF Plus BPL 2A 2 4 Branch IFF Minus BMI 2B 2 4 Branch IFF Interrupt Mask Bit is Clear BMC 2C 2 4 Branch IFF Interrupt Mask Bit is Set BMS 2D 2 4 Branch IFF Interrupt Line is Low BIL 2E 2 4 Branch IFF Interrupt Line is High BIH 2F 2 4 Branch to Subroutine BSR AD 2 8 Table 10 4 Bit Manipulation Instructions Addressing Modes Bit SetlClear Bit Test and B...

Page 68: ... NOP 9D 1 2 Table 10 6 Instruction Set Sheet 1 of 2 Addressing Modes I Bit I Indexed Indexed Indexed Setl I Mneml Inherent Immediate Direct Extended Relative No Offset 8 Bits 16 Bits Clear ADC X ADD X AND X ASL X ASR X BCC BCLR BCS BEQ BHCC BHCS BHI BHS BIH BIL BIT X BLO BLS BMC BMI BMS BNE BPL BRA Condition Code Symbols H Half Carry From Bit 3 I Interrupt Mask N Negative Sign Bit Z Zero X X I X X...

Page 69: ...gn Bit Z Zero Table 10 6 Instruction Set Sheet 2 of 2 Addressing Modes Indexed Indexed Direct Extended Relative No Olfset 8 Bits X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X i X X X X X X X X X X X X X X X X X C Carry Borrow Test and Set if True Cleared Otherwise Not Affected Load CC Register From Stack 10 9 Indexed 16 Bits X...

Page 70: ... A I X 2 IXI I IX 10 5 7 5 4 3 6 5 4 3 4 3 7 6 6 5 S BRSET4 BSET4 BHCC LSL LSL LSL LSL LSL 1000 3 BTB 2 BSC 2 REL 2 DIR I A I X 2 IXI I IX 10 5 7 5 4 3 6 5 4 3 4 3 7 6 6 5 9 BRCLR4 BCLR4 BHCS ROL ROL ROL ROL ROL 1001 3 BTB 2 BSC 2 REL 2 DIR I A I X 2 IXI I IX 10 5 7 5 4 3 6 5 4 3 4 3 7 6 6 5 A BRSET5 BSET5 BPL DEC DEC DEC DEC DEC 1010 3 BTB 2 BSC 2 REL 2 DIR I A X 2 IXI I IX 10 5 7 5 4 3 B BRCLR5 ...

Page 71: ...A STA STA 7 1 INH 2 DIR 3 EXT 3 IX2 2 IXl 1 IX 0111 2 2 2 2 4 3 5 4 6 5 5 4 4 3 CU EOR EOR EOR EOR EOR EOR 8 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IXl 1 IX 1 0 2 2 2 2 4 3 5 4 6 5 5 4 4 3 SEC ADC ADC ADC ADC ADC ADC 9 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IXl 1 IX 1001 2 2 2 2 4 3 5 4 6 5 5 4 4 3 CLI ORA ORA ORA ORA ORA ORA A 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IXl 1 IX 1010 2 2 2 2 4 3 5 4 6 5 5 4 4 3 SEI ADD AD...

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Page 73: ...3V 40 to 105 Storage Temperature Range TstQ 55 to 150 c Junction Temperature Plastic 150 Ceramic TJ 175 C W Cerdip 175 11 2 THERMAL CHARACTERISTICS Characteristic Symbol Value Unit Thermal Resistance Plastic P Suffix MC6805R2 MC6805U2 MC6805R3 MC6805U3 60 Ceramic MC6805R2 MC6805U2 MC6805R3 JJA C W MC6805U3 MC68705R3 MC68705U3 50 MC68705R5 MC68705U5 Cerdip MC6805R2 MC6805U2 MC6805R3 MC6805U3 MC6870...

Page 74: ...p between Po and TJ if PPORT is neglected is PO K TJ 273 2 Solving equations 1 and 2 for K gives K Poe TA 273 C 8JAePo2 3 Where K is a constant pertaining to the particular part K can be determined from equation 3 by measuring Po at equilibrium for a known TA Using this value of K the values of Po and TJ can be obtained by solving equations 1 and 2 iteratively for any value of TA VCC 5 75V Figure ...

Page 75: ...hrough a Capacitor VINT 2 Power Dissipation No Port Loading VCC 5 75 V TA O C PD for Steady State Operation TA 40 C Input Capacitance XTAL Cin All Other Except Analog Inputs See Note Low Voltage Recover VLVR Low Voltage Inhibit VLVI 2 75 Input Current TIMER Vin O 4 INT Vin 2 4 V to VCC EXTAL Vin 2 4 V to VCC Crystal Option lin Vin O 4 V Crystal Option RESET Vin O S V IRES 4 0 External Capacitor Ch...

Page 76: ...25 Vdc O 5 Vdc VSS O Vdc TA TL to TH unless otherwise noted Min Typ Max Unit Comments Resolution 8 8 8 Bits Non Linearity 1 2 LSB For VRH 4 0 to 5 0 V and VRL 0 V Quantizing Error 1 2 LSB Conversion Range VRL VRH V VRH VCC V AID accuracy may decrease proportionately as VRL VSS 0 2 V VRH is reduced below 4 0 V The sum of VRH and VRL must not exceed VCe Conversion Time 30 30 30 tcyc Includes samplin...

Page 77: ...n Current Drive Source VO 1 5 V IOH 1 0 10 mA Input High Voltage VIH 2 0 VCC V Input Low Voltage VIL VSS 0 8 V Hi Z State Input Current ITSI 2 10 I A Port C and Port A with CMOS Device Disabled Ouput Low Voltage ILoad 1 6 mA VOL 0 4 V Output High Voltage ILoad 100 I A VOH 2 4 V Input High Voltage VIH 2 0 VCC V Input Low Voltage VIL VSS 0 8 V Hi i State Input Current ITSI 2 10 I A Port C Open Drain...

Page 78: ...S0 SOO Input Capacitance XTAL Cin 25 pF All Other 10 Low Voltage Recover VLVR 4 75 V Low Voltage Inhibit VLVI 2 75 3 75 4 70 V Input Current TIMER Vin Oo4 V 20 INT Vin 2 4 V to VCC 20 50 EXTAL Vin 204 V to VCC Crystal Option lin 10 p A __ Vin Oo4 V Crystal Option 1600 RESET Vin O S V IRES 4 0 40 External Capacitor Charging Current Due to internal biasing this input when unused floats to approximat...

Page 79: ...mA VOl 0 4 V Output Low Voltage ILoad 10 mA sink VOL 1 0 V Output High Voltage ILoad 200 I A VOH 2 4 V Darlington Current Drive Source VO 1 5 V 10H 1 0 10 mA Input High Voltage VIH 2 0 Vr r V Input Low Voltage VIL VSS 0 8 V Hi Z State Input Current ITSI 2 10 I A Port C and Port A with CMOS drive disabled Output Low Voltage ILoad 1 6 mA VOL 0 4 V Output High Voltage ILoad 100 I A IoH 2 4 V Input Hi...

Page 80: ...er VSS 0 8 V INT Zero Crossing Input Voltage Through a Capacitor VI NT 2 0 4 0 Vac p p Internal Power Dissipation No Port Loading VCC 5 25 V TA O C PINT 520 740 mW for Steady State Operation TA 40 C 580 800 Input Capacitance EXTAL Cin 25 pF All Other See Note 10 pF RESET Hysteresis Voltage See Figure 7 1 Out of Reset Voltage VIRES 2 1 4 0 V Into Reset Voltage VIRES 0 8 2 0 V Programming Voltage Vp...

Page 81: ... 4 AID Converter Characteristics VCC 5 25 V O 5 Vdc VSS O Vdc TA O to 70 C unless otherwise noted Characteristic Min Typ Max Unit Comments Resolution 8 8 8 Bits Non Linearity I 1 2 LSB For VRH 4 0 to 5 0 V and VRL 0 V Quantitizing Error 1 2 LSB Conversion Range VRL VRH V VRH VCC V A D accuracy may decrease proportionately as VRL VSS 0 2 V VRH is reduced below 4 0 V The sum of VRH and VRL must not ...

Page 82: ...ve Source VO 1 5 V IOH 1 0 10 mA Input High Voltage V H 2 0 VCC V Input Low Voltage V L VSS 0 8 V Hi Z State Input Current TS 2 10 p A Port C Output Low Voltage Load 1 6 mA VOL 0 4 V Output High Voltage Load 100 p A VOH 2 4 V Input High Voltage V H 2 0 VCC V Input Low Voltage V L VSS 0 8 V Hi Z State Input Current TS 2 10 p A Port D Input Only Input High Voltage V H 2 0 VCC V Input Low Voltage V L...

Page 83: ...VCC 5 75 Input Current TIMER Vin 0 4 V 20 INT Vin O 4 V 20 50 EXTAl Vin 2 4 V to VCC Crystal Option lin 10 p A Vin 0 4 V Crystal Option 1600 RESET Vin 0 8 V IRES 4 0 40 External Capacitor Changing Current Vpp is Pin 7 on the MC68705U3 and MC68705U5 and is connected to VCC in the Normal Operating Mode In the MC6805U2 Pin 7 is NUM and is connected to VSS in the Normal Operating Mode The user must al...

Page 84: ...State Input Current ITSI 2 10 LA Port 0 Input Only Input High Voltage VIH 2 0 VCC V Input Low Voltage VIL VSS 0 8 V Input Current lin 1 5 LA 11 8 I O CHARACTERISTICS Figures 11 5 through 11 15 illustrate I O characteristic data for HMOS M6805 Family devices Simplified port logic diagrams are shown in Figures 11 16 and 11 17 typical input protection in Figure 11 18 and an I O characteristic measure...

Page 85: ...CI I MIN I 1 121121 TYPICAL EXPECTEO EXPECTED MIN 25 C MAX 1 85 C 4 75V 2 121121 3 121121 VOH VOLTS S 25V I 40 C S 7SV I J 4 121121 Figure 11 5 Port A VOH vs IOH with CMOS Pull ups EXPECTED MAX 5 75V 400C TYPICAL 5 25V 5 121121 6 121121 25 C XPECTED L 5V I 85 C 0 4V l 6mA VY 1121 X SPEC PT 2121 3121 VOL VOLTS 4121 Figure 11 6 Port A VOL vs IOL with CMOS Pull ups 11 13 5121 8121 ...

Page 86: ...C MAX S 7SV 40 C S 5e 4 5e V 5 5e e ee 1 ee 2 ee s ee vaH VOLTS 4 ee 5 ee 12 ee le ee s ee e ee 4 ee 2 ee e ee e ee Figure 11 7 Port B VOH VS IOH XPECTE TYPICAL MAX S 2SV S 7SV 25 C 400C VEXPECTED MIN 4 7SV I 8SOC V O 4V 3 2mA j A le X SPEC PT 2e se VOL VOLTS 4e Figure 11 8 Port B VOL vs IOL 11 14 5e 6 ee 5e ...

Page 87: ...5 25V I 1 121121 I 2 121121 a 12I121 VOH VOLTS I I I 4 121121 Figure 11 9 Port C VOH vs IOH Port A Without CMOS Pull ups EXPECTED MAX 40 C 5 7SV 5 121121 6 121121 12 121121 ___ ______ ______ ________ ________ ______ 1121 x SPEC PT 211S aIlS VOL VOLTS 4 lIS Figure 11 10 Port C VOL vs IOL Port A Without CMOS Pull ups 11 15 511S 6121 ...

Page 88: ...C PT 1 00 1 50 VIN VOLTS Figure 11 11 Port A Vin vs lin with CMOS Pull ups 2 50 3 00 50 r 25 r r _ EXPECTED MIN 4 75V 0 00 ________ ________ _ 85 o C _ 25 __ _ _ TYPICAL i5 50 _ _ _ __ _ ___ EXPECTED _ MAX 5 75V _ 75 __________ _ r 40 O C 1 00r r _ r_ _ 1 25r r r_ _ 1 50 O 4V 1 6mA X 1 75 0 00 1 00 2 00 3 00 4 00 5 00 6 00 VIN VOLTS x SPEC PT Figure 11 12 EXTAL Vin vs lin 11 16 ...

Page 89: ..._ _4 40 00r r r _4 _ O 4V SO lA 1 00 X SPEC PT 2 00 S 00 VIN VOLTS 4 00 Figure 11 13 Interrupt Vin vs lin 5 00 6 00 50 00r r 40 00r 4 _ _ 30 00 4_ _ _ 20 00 _ 3 10 00 _ _ Z H EXPECTED 0 00 O 8 V 4 l A M I N 4 7 S V 8 _C __ X _10 00 F _ _ _ _ _ Tvp icAL S 2SV 20 00r 2S 0 C __ 4 E X PE C TE D 4 1 MAX S 7SV 4ooC 30 00 _ _ 40 00 _ _1 O 8V SOIlA 50 00 L_ L L L L 0 00 1 00 2 00 3 00 4 00 5 00 6 00 VIN V...

Page 90: ... DEVICE Qe eer r_ _ r r L 1 t ee 121121 I ae ee ____ ____ __ 4 __ _ __ __ r __ __ __ e ee ____ ____ ______ ______ ______ ______ ______ ______ 4 121121 4 25 4 5121 4 75 S 121121 S 25 s 5121 S 75 e 121121 VOO VOLTS TA 4I21C TA aile Tit a c Figure 11 15 VOO vs 100 Variation with Temperature 11 18 ...

Page 91: ...PortA CMOS k Pullup Option I Figure 11 16 Ports A and C Logic Diagram PAD A V v To I O Logic Figure 11 18 Typical Input Protection VDD 1 10 k Typ PB DDR PB Data IP Input Protection Figure 11 17 Port B Logic Diagram V Vary V Measure I Figure 11 19 I O Characteristic Measurement Circuit 11 19 11 20 ...

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Page 93: ...ix Plastic P Suffix Cerdip S Suffix Temperature O C to 70 C 40 C to 85 C O C to 70 C 40 C to 85 C O C to 70 C 40 C to 85 C Temperature O C to 70 C 40 C to 85 C O C to 70 C 40 C to 85 C O C to 70 C 40 C to 85 C Temperature O C to 70 C 40 C to 85 C O C to 70 C 40 C to 85 C O C to 70 C 40 C to 85 C 12 1 Generic Number MC6805R2L MC6805R2CL MC6805R2P MC6805R2CP MC6805R2S MC6805R2CS Generic Number MC680...

Page 94: ...C to 85 C MC68705U3CL 12 8 MC68705U5 Package Type Temperature Generic Number Ceramic O C to 70 C MC68705U5L L Suffix 40 C to 85 C MC68705U5CL Cerdip O C to 70 C MC68705U5S S Suffix 40 C to 85 C MC68705U5CS 12 9 CUSTOM MCUs The information required when ordering a custom MCU is listed below The ROM program may be transmitted to Motorola on EPROM s or an MDOS disk file To initiate a ROM pattern for ...

Page 95: ...and tested only at room temperature and 5 volts These RVUs are included in the mask charge and are not production parts Therefore the RVUs are not guaranteed by Motorola Quality Assurance and should be discarded after verification is completed 12 9 4 Flexible Disk The disk media submitted must be single sided single density 8 inch MOOS compatible floppies The customer must write the binary file na...

Page 96: ...MOS and TTL o TTL Only Low Voltage Inhibit o Disable o Enable Port C Output Drive o TTL o Open Drain Timer Clock Source MC6805R2 U2 Only o Internal jJ2 clock o TIMER input pin Pattern Media All other media requires prior factory approval o EPROMs MCM2716 or MCM2532 o Floppy Disk Timer Prescaler MC6805R2 U2 Only o 20 divide by 1 o 21 divide by 2 o 22 divide by 4 o 23 divide by 8 o 24 divide by 16 o...

Page 97: ...6 INT 3 PA5 INT 3 PA5 VCC 4 PA4 VCC 4 PA4 EXTAL 5 PA3 EXTAL 5 PA3 PA2 PA2 VSS NUM 7 PAl NC 7 PAl TIMER 8 PAD TIMER 8 PAD PCO 9 PB7 PCO 9 PB7 PCl 10 PB6 PCl 10 PB6 PC2 11 PB5 PC2 11 PB5 PC3 12 PB4 PC3 12 PB4 PB3 PC4 PB3 PC5 PB2 PC5 PB2 PC6 PBl PC6 PBl PC7 16 PBO PC7 PBO P07 POO ANO P07 POO ANO P06 1NT2 P011ANl P06 1NT2 PD1 AN1 PD5IVRH 19 PD2 AN2 PD5IVRH PD2 AN2 PD4IVRL 20 P03 AN3 PD4IVRL PD3 AN3 13...

Page 98: ...TAL PA2 XTAL 6 PA2 VSS NUM 7 PAl NC 7 PAl TIMER PAO TIMER 8 PAO PCO PB7 PCO 9 PB7 PCl PB6 PCl 31 PB6 PC2 11 PB5 PC2 11 PB5 PC3 PB4 PC3 12 PB4 PC4 PB3 PC4 28 PB3 PC5 PB2 PC5 14 PB2 PC6 PB1 PC6 26 PB1 PC7 PBO PC7 25 PBO PD7 PDO PD7 24 PDO PD6 1NT2 PDl PD6 1NT2 23 PDl PD5 PD2 PD5 22 PD2 PD4 PD3 PD4 21 PD3 13 2 ...

Page 99: ...PA3 PA3 XTAL 6 PA2 PA2 VPP PAl VPP PAl TIMER 8 PAG PAO PCO 9 PB7 PBl PCl 10 PS6 PB6 PC2 11 PB5 PB5 PC3 12 PS4 PC3 PB4 PC4 13 PB3 PC4 PB3 PC5 14 PB2 PC5 PB2 PC6 lb PBl PC6 PBl PC7 16 PSO PCl PBO PD7 17 POOl ANO P07 POO P06 1NT2 18 P01 AN1 P06 iNTI POl P05IVRH 19 P021 AN2 P05 P02 P04IVRL 20 21 P031 AN3 P03 13 3 ...

Page 100: ...J 0 20 0 33 0 008 0 013 K 2 54 4 57 0 100 0 180 L 14 99 15 65 0 590 0 616 M 100 100 N 1 02 1 52 0 040 0 060 13 2 2 Ceramic MC68705R3 MC68705R5 MC68705U3 MC68705U5 L SUFFIX CERAMIC PACKAGE CASE 715 06 It A f 13 4 NOTES 1 DIMENSIONW IS DATUM 2 POSITIONAL TOLERANCE FOR LEADS 10 25 0 010 e T Ael 3 III IS SEATING PLANE 4 DIMENSION LuTO CENTER OF LEADS WHEN FORMED PARALLEL 5 DIMENSIONING AND TOLERANCING...

Page 101: ...94 5 08 0 155 0 200 D 0 36 0 56 0 014 0 022 F 1 02 1 52 0 040 0 060 G 2 54 BSC 0 100 BSC H 1 65 2 16 0 065 0 085 J 0 20 0 38 0 008 0015 K 2 92 I 3 43 0 115 0 135 L 15 24 BSC 0 600 BSC M 0 15 0 15 N 0 51 I 1 02 0 020 0 040 NOTES 1 DIM A IS DATUM 2 POSITIONAL TOLERANCE FOR LEADS 1 t190 25 0 010 81 T IA 81 3 JJ IS SEATING PLANE 4 DIM L TO CENTER OF LEADS WHEN FORMED PARALLEL 5 DIMENSIONS A AND B INCL...

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Page 104: ... MOTOROLA Semiconductor Products Inc 3501 ED BLUESTEIN BLVD AUSTIN TEXAS 78721 A SUBSIDIARY OF MOTOROLA INC ...

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