4.1 - 34
MTP700 Portable Radio / Detailed Service Manual
TRANSCEIVER 400 MHz
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REDCAP2
DNP
64Mb_SEL
SPIB
DNP
FLASH
NU
GCAP3_INT
PTT
SPIA
DISPLAY_RS
17x17mm BGA
SRAM
NU
GCAP3
EMERGENCY
Option_Select_2
Option_Select_1
7
11
OPT_SEL_2
KP_COL3
SW_1
INTERRUPT INPUTS
Internal Pulldown
.01uF
PTT
RESET_OUT
16
C305
TP316
17
SPIA_CLK
32KHz_CLK
TP301
V3_2.775V_DIG
21
SPIB_MOSI
11
15
SPIB_CLK
KP_COL4
12
TP305
TP306
GCAP3_DCLK
WPIC_TXCLK
4
S_EN
V3_2.775V
WPIC_TXE
KP_COL2
SOFT_TURN_OFF
BAT_DATA_PULL_UP
14
HEADSET_KEYFAIL
GCAP3_RX
WPIC_STD
39K
R307
R308
5
SPIA_MISO
GCAP3_STANDBY
SW_2
39K
10
9
SW_8
SW_4
39K
R115
DISPLAY_RS
TX_DETECT
SIDE_TX
SIDE_OPT_SEL1
2
1
_EN
0.1uF
C026
1
19
FILT_3.3V
R006
39K
LV_DETECT
KP_COL0
SIDE_CTS
4
SW_1
SIDE_OPT_SEL2
5
VIBRATOR
SIDE_RX
7
GCAP3_TX
OPT_SEL_1
V3_2.775V_DIG
KP_ROW3
PWM1_1.8V
3
TP312
TP300
R008
39K
39K
IDLE
R007
VCC
5
R324
39K
NL27WZ16
U001
GND
2
IN_A1
1
IN_A2
3
OUT_Y1
6
OUT_Y2
4
1K
R001
16.8_MHz_CLK
10
6
OUT_Y1
4
OUT_Y2
5
VCC
C306
10uF
U002
NL27WZ16
2
GND
1
IN_A1
3
IN_A2
6
TP302
39K
R313
SPIA_CS2_ODCT
SPIA_MOSI
15
TETRA_MAIN_VCO_ON
BAT_DATA_OUT
20
AUDIO_PA_ENABLE
SPIA_CS1_ESCORT
14
18
KP_COL1
KP_ROW0
SPIA_CS0_WPIC
6800pF
220nH
13
GCAP3_FSYNC
C304
SIDE_RTS
L301
6
5
C027
0.1uF
39K
R009
33pF
C330
GCAP3_INT
C331
33pF
KP_ROW1
BAT_DATA_IN
ESC_VCO_BUF_EN
22K
R314
XYD9
C4
XZYRW
XYSEL
B5
B4
XYST
TP335
XYD2
M5
XYD3
P8
XYD4
R8
XYD5
T8
XYD6
N8
XYD7
M6
L10
XYD8
M9
D1
XYD0
R7
XYD1
T7
M10
XYD10
M11
XYD11
N9
XYD12
T9
XYD13
R9
XYD14
XYD15
P9
B3
XYA2
B2
XYA3
A3
XYA4
A2
XYA5
A1
XYA6
C2
XYA7
XYA8
C3
XYA9
A4
XYA0
D4
XYA1
XYA10
D2
XYA11
D3
XYA12
E2
XYA13
E1
XYA14
E3
E4
XYA15
TOUT5
A6
TOUT6
D6
TOUT7
D7
C7
TOUT8
B7
TOUT9
TRST
H14
TXA_TDO
G15
K11
TXB
A8
TOUT11
D8
TOUT12
E6
TOUT13
E7
TOUT14
E8
TOUT15
TOUT2
D5
TOUT3
C6
TOUT4
B6
T13
TCK
H13
TDI
G12
TDO
F12
TEST
G16
TMS
H12
TOUT0
A5
TOUT1
C5
B8
TOUT10
E12
SPI_CKA
A9
D11
SPI_CKB
SRDA
D13
SRDB
B14
B12
SRDB2
STDA
D16
STDB
A14
STO
SPICS0B
SPICS1A
E11
C10
SPICS1B
SPICS2A
E10
B10
SPICS2B
SPICS3A
E9
A10
SPICS3B
SPICS4A
F7
SPICS4B
P12
SENSE
SIMCLK
N11
SIMDATA
N12
SIMRESET
T12
SIZ0
F15
SIZ1
F14
SPICS0A
D9
D10
SC0A
SC0B
B13
SC1A
A16
SC1B
A13
SC2A
A15
SC2B
C14
SCKA
C15
SCKB
C13
A12
SCKB2
ROW5_IC2B
ROW6_DCD_SC2A_DSP_DE
J16
ROW7_RI_SCKA_TCK
J13
RTSA_IC2A_RESET_IN
G13
RTSB
K12
RW
M2
RXA_IC1_TDI
G14
J12
RXB
B16
PWR_EN
RESET_IN
R13
RESET_OUT
P13
ROW0
L15
K13
ROW1
ROW2
K14
ROW3
K15
ROW4
J14
J15
P1GND
PCAP
R10
PGND
P10
PSTAT0
E13
E15
PSTAT1
D14
PSTAT2
PSTAT3
D15
PVCC
T10
T11
MCU_DE
MISOA
B9
C11
MISOB
MOD
R12
MOSIA
C9
D12
MOSIB
MUX_CTL
F16
OE
M1
N10
INT0
INT1
N15
INT2
N14
INT3
M15
INT4
M16
INT5
M14
INT6_DSR_STDA_TRST
M13
INT7_DTR_SCLK_SRDA_TMS
L14
H11
D7
P4
D8
P5
D9
N5
DSP_DE
G11
DSP_IRQ
C12
EB0
K1
EB1
J3
N16
D13
N6
D14
N7
D15
P7
D2
T3
R3
D3
D4
P3
D5
T4
D6
R4
CS4
CS5
R1
CTSA_MCU_DE
F13
L12
CTSB
D0
T1
T2
D1
D10
P6
D11
R6
D12
T6
COLUMN4
COLUMN5
P16
COLUMN6_OC1
P15
COLUMN7
P14
CS0
N3
CS1
N2
CS2
P2
CS3
R2
P1
CKIH
K2
CKIL
CKO
M3
CKOH
L2
COLUMN0
N13
COLUMN1
R14
COLUMN2
R15
COLUMN3
T14
R16
ADDR21
L5
ADDR3
ADDR4
K6
ADDR5
J6
ADDR6
H6
ADDR7
G6
ADDR8
H5
ADDR9
G5
K4
ADDR14
E5
ADDR15
ADDR16
G3
ADDR17
G4
ADDR18
F4
ADDR19
F1
ADDR2
J4
ADDR20
F2
F3
ADDR0
J2
ADDR1
J1
ADDR10
F5
ADDR11
H4
ADDR12
H1
ADDR13
H2
H3
1
RX_ACQ
SPIA_CS_PA_BIAS
30C40
U301-1
0
SPIB_CS2_GCAP3
6
0
13
12
WPIC_FSYNC
PA_BIAS
GCAP3_AD_TRIGGER
SYNT_CS_
WPIC_OSC_EN
SPIB_MISO
ANT_EN
3
8
SPIB_CS1_DISPLAY
EMERGENCY
2
TP307
1K
R002
3
2
MOD
9
TP304
TP303
KP_ROW4
KP_ROW2
WPIC_SRD
LO_DRIVER_EN
4
8
EXT_SPKR_SEL
R312
E302
DSP_3
MEM_CNTL(6:1)
HST_Addr(0:21)
HST_Addr(0:21)
51
HST_DATA(0:15)
HST_DATA(0:15)
RS232_DTR
RS232_DSR
RS232_CTS
DSP_1
RS232_RX
RS232_RTS
RS232_RI
RS232_DCD
MUX_CTRL
RS232_TX
DSP, Controller & Memory Schematic Diagram (RedCap2)
Summary of Contents for IMPRES Tetra MTP700
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