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Motorola DragonBall MC68328 User Manual Download Page 108

 

UART 

 

MOTOROLA

 

MC68328 DRAGONBALL PROCESSOR USER’S MANUAL

 

8-5

 

interrupt sources. While the UART EN bit is low, the master clock to all UART blocks is dis-
abled, reducing power consumption to a minimum.

 

8.2.5 UART Control Register

 

This register controls the overall UART operation. This register resets to $0000.

UART ENABLE

This bit enables the UART. While this bit is low, the UART is disabled and in low-power
mode. While this bit is high, the UART is active. This bit resets to 0.

0 = UART disabled
1 = UART enabled

 

NOTE

 

When the UART is first enabled after cold reset, before enabling
interrupts, set the UART ENABLE and RX ENABLE bits and per-
form a word-read operation on the receiver register to initialize
the FIFO and character-status bits.

RX ENABLE

This bit enables the receiver block. While this bit is low, the receiver is disabled and the
receive FIFO is flushed. This bit resets to 0.

0 = Receiver disabled and receive FIFO flushed
1 = Receiver enabled

TX ENABLE

This bit enables the transmitter block. While this bit is low, the transmitter is disabled and
the transmit FIFO is flushed. This bit resets to 0.

0 = Transmitter disabled and transmit FIFO flushed
1 = Transmitter enabled

RX CLK CONT

Receiver Clock Control

This bit controls the receiver operating mode of the receiver. While low, the receiver is in
16x mode where it synchronizes to the incoming data stream and samples at the per-
ceived center of each bit period. While high, the receiver is in 1x mode where it samples
the data stream on each rising edge of the bit clock. This bit resets to 0.

0 = 16x clock mode
1 = 1x clock mode

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

UART 

ENABLE

RX 

ENABLE

TX 

ENABLE

RX CLK 

CONT

PARITY 

EN

ODD 

EVEN

STOP 

BITS

8/7

GPIO 

DELTA 

ENABLE

CTS 

DELTA 

ENABLE

RX FULL

ENABLE

RX 

HALF 

ENABLE

RX RDY 

ENABLE

TX 

EMPTY 

ENABLE

TX HALF 

ENABLE

TX 

AVAIL 

ENABLE

ADDRESS: $(FF)FFF900

Reset Value: $0000

 

Figure 8-2. UART Control Register

Summary of Contents for DragonBall MC68328

Page 1: ...d for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify an...

Page 2: ...lease do not fax technical questions Please provide the part number and revision number located in upper right hand corner of the cover and the title of the document When referring to items in the manual please ref erence by the page number paragraph number figure number table number and line num ber if needed When sending a fax please provide your name company fax number and phone number includin...

Page 3: ...TARIO Toronto 416 497 8181 ONTARIO Ottawa 613 226 3491 QUEBEC Montreal 514 731 6881 INTERNATIONAL AUSTRALIA Melbourne 61 3 887 0711 AUSTRALIA Sydney 61 2 906 3855 BRAZIL Sao Paulo 55 11 815 4200 CHINA Beijing 86 505 2180 FINLAND Helsinki 358 0 35161191 Car Phone 358 49 211501 FRANCE Paris Vanves 33 1 40 955 900 GERMANY Langenhagen Hanover 49 511 789911 GERMANY Munich 49 89 92103 0 GERMANY Nurember...

Page 4: ...28 The organization of this manual is as follows Section 1 Overview Section 2 System Integration Module Section 3 Phase Locked Loop and Power Control Section 4 LCD Controller Module Section 5 Real Time Clock Module Section 6 Timer Module Section 7 Parallel Ports Section 8 Universal Asynchronous Receiver Transmitter UART Module Section 9 Serial Peripheral Interfact Slave SPIS Section 10 Serial Peri...

Page 5: ...vi MC68328 DRAGONBALL PROCESSOR USER S MANUAL MOTOROLA ...

Page 6: ...Purpose I O Ports 1 9 1 2 2 7 Software Watchdog 1 9 1 2 2 8 Low Power Stop Logic 1 9 1 2 3 LCD Controller 1 9 1 2 4 UART and Infrared Communication Support 1 9 1 2 5 Real Time Clock 1 9 1 2 6 JTAG Test Access Port 1 10 1 2 7 SIM28 Programming Model 1 10 Section 2 System Integration Module 2 1 Module Operation 2 1 2 1 1 MC68328 Processor System Configuration 2 1 2 1 1 1 System Control Register Func...

Page 7: ...ction 3 Phase Locked Loop and Power Control 3 1 Overview 3 1 3 2 Programmer s Model 3 1 3 2 1 PLL Control Register 3 2 3 2 2 Frequency Select Register 3 2 3 3 PLL Operation 3 3 3 3 1 Initial Powerup 3 3 3 3 2 Divider 3 3 3 3 3 Normal Startup 3 4 3 3 4 Change of Frequency 3 4 3 3 5 PLL Shutdown 3 4 3 4 Power Control Module Overview 3 5 3 4 1 Description 3 5 3 4 2 MPU Interface 3 7 3 4 3 Operation 3...

Page 8: ...or X Position Register CXP 4 14 4 7 3 2 Cursor Y Position Register CYP 4 14 4 7 3 3 Cursor Width Height Register CWCH 4 15 4 7 3 4 Blink Control Register BLKC 4 15 4 7 4 LCD Panel Interface Registers 4 15 4 7 4 1 Panel Interface Configuration Register PICF 4 15 4 7 4 2 Polarity Configuration Register POLCF 4 16 4 7 4 3 LACD M Rate Control Register ACDRC 4 17 4 7 5 Line Buffer Control Registers 4 1...

Page 9: ...1 General Purpose Timer 6 4 6 4 1 1 Counter Register 6 4 6 4 1 2 Timer Control Registers 6 4 6 4 1 3 Timer Prescaler Register 6 5 6 4 1 4 Timer Compare Register 6 5 6 4 1 5 Timer Capture Register 6 6 6 4 1 6 Timer Status Register 6 6 6 4 2 Software Watchdog Timer 6 7 6 4 2 1 Watchdog Compare Register 6 7 6 4 2 2 Watchdog Counter Register 6 7 6 4 2 3 Watchdog Control Status Register WCR 6 7 Section...

Page 10: ...ection 9 Serial Peripheral Interface SLAVE SPIS 9 1 Overview 9 1 9 2 Operation 9 1 9 3 Signal Descriptions 9 2 9 4 SPIS Register 9 2 9 4 1 SPI Slave Register 9 3 Section 10 Serial Peripheral Interface Master SPIM 10 1 Overview 10 1 10 2 Operation 10 1 10 2 1 Operation within SPIM Module 10 1 10 2 2 Phase Polarity Configurations 10 2 10 3 Signal Descriptions 10 2 10 4 SPIM Registers 10 3 10 4 1 SPI...

Page 11: ... USER S MANUAL MOTOROLA Section 12 Pin Assignment Section 13 Electrical Characteristics 13 1 Maximum Ratings 13 1 13 2 Power Consumption 13 1 13 3 AC Electrical Specification Definitions 13 1 13 4 AC Electrical Specifications Read and Write Cycles 13 1 ...

Page 12: ...nsmitter UART and the system integration module SIM28 give the system engineer more flexibility and resources to design efficient and innovative products 1 1 KEY FEATURES The primary features of the MC68328 processor illustrated in Figure 1 are as follows MC68EC000 Static Core Processor 100 Compatibility with MC68000 And MC68EC000 Processors 24 Bit External and 32 Bit Internal Address Bus Optional...

Page 13: ... 67 MHz System Clock Each Timer Has an Input and an Output Pin for Capture and Compare Pulse Width Modulation Output for Sound Generation Programmable Frame Rate 16 Bit Programmable Supports Motor Control Real Time Clock 24 Hour Time 1 Programmable Alarm Figure 1 MC68328 Block Diagram DUAL 16 BIT TIMER MODULE PWM MODULE MC68EC000 HCMOS STATIC CORE UART WITH INFRA RED SUPPORT SLAVE SPI MASTER SPI L...

Page 14: ... to address specific applications but are often use ful in a variety of applications The peripherals may be highly sophisticated timing or protocol engines that have their own processors or they may be more traditional peripheral functions such as UARTs and timers 1 1 2 ADVANTAGES The many features incorporated into a single M68300 Family chip help system designers realize significant savings in d...

Page 15: ...els operating systems languages applications and development tools 1 2 1 1 EC000 CORE PROGRAMMING MODEL The EC000 core offers sixteen 32 bit registers and a 32 bit program counter see Figure 1 1 The first 8 registers D7 D0 serve as data registers for byte 8 bit word 16 bit and long word 32 bit operations Because using data registers will affect the condition code register which indicates negative ...

Page 16: ...listed in Table 1 1 include six basic types 1 Register direct 2 Register indirect 3 Absolute 4 Program counter relative Figure 1 1 User Programming Model Figure 1 2 Supervisor Programmer s Model Supplement DATA REGISTERS ADDRESS REGISTERS 31 16 15 8 7 0 USER STACK POINTER A7 USP D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 0 15 16 31 31 16 15 0 31 0 0 PC PROGRAM COUNTER STATUS REGISTER CCR 7 SUPER...

Page 17: ...N MODULE The MC68328 SIM28 consists of several functions that control the system startup initializa tion configuration and the external bus with a minimum of external devices The memory Table 1 1 Address Modes Address modes Syntax Register direct address Data register direct Address register direct Dn An Absolute data address Absolute short Absolute long xxx W xxx L Program counter relative addres...

Page 18: ...HG Bit test and change NOT Ones complement BCLR Bit test and clear OR Logical OR BRA Branch always ORI OR immediate BSET Bit test and set ORI to CCR OR immediate to condition codes BSR Branch to subroutine ORI to SR OR immediate to status register BTST Bit test PEA Push effective address CHK Check register against bounds RESET Reset external devices CLR Clear operand ROL Rotate left without extend...

Page 19: ... processor provides 16 programmable gen eral purpose chip select signals For a given chip select block users may choose 1 whether the chip select allows read only or both read and write accesses 2 whether a DTACK is automatically generated for this chip select and 3 the number of wait states from zero to six until the DTACK will be generated 1 2 2 4 EXTERNAL BUS INTERFACE The external bus interfac...

Page 20: ...GIC Various power save options are available turn off unused peripherals reduce processor clock speed disable the processor altogether or a combination of these A wake up from low power mode can be achieved by an interrupt at the interrupt controller logic that runs throughout the period of processor low power Programmable interrupt sources can serve as events to wake up the EC000 core The on chip...

Page 21: ...Overview 1 10 MC68328 DRAGONBALL PROCESSOR USER S MANUAL MOTOROLA 1 2 7 SIM28 Programming Model The SIM28 programming model is listed in Table 1 3 ...

Page 22: ... C Chip Select 2 Register 00010006 Base 13C CSC3 32 CS Group C Chip Select 3 Register 00010006 Base 140 CSD0 32 CS Group D Chip Select 0 Register 00010006 Base 144 CSD1 32 CS Group D Chip Select 1 Register 00010006 Base 148 CSD2 32 CS Group D Chip Select 2 Register 00010006 Base 14C CSD3 32 CS Group D Chip Select 3 Register 00010006 Base 200 PLLCR 16 PLL PLL Control Register 2400 Base 202 PLLFSR 1...

Page 23: ... Select Register FF Base 500 PWMC 16 PWM PWM Control Register 0000 Base 502 PWMP 16 PWM PWM Period Register 0000 Base 504 PWMW 16 PWM PWM Width Register 0000 Base 506 PWMCNT 16 PWM PWM Counter 0000 Base 600 TCTL1 16 Timer Timer Unit 1 Control Register 0000 Base 602 TPRER1 16 Timer Timer Unit 1 Prescalar Register 0000 Base 604 TCMP1 16 Timer Timer Unit 1 Compare Register FFFF Base 606 TCR1 16 Timer...

Page 24: ... LCDC Blink Control Register 7F Base A20 LPICF 8 LCDC Panel Interface Config Register 00 Base A21 LPOLCF 8 LCDC Polarity Config Register 00 Base A23 LACDRC 8 LCDC ACD M Rate Control Register 00 Base A25 LPXCD 8 LCDC Pixel Clock Divider Register 00 Base A27 LCKCON 8 LCDC Clocking Control Register 40 Base A29 LLBAR 8 LCDC Last Buffer Address Register 3E Base A2B LOTCR 8 LCDC Octet Terminal Count Reg...

Page 25: ...Overview 1 14 MC68328 DRAGONBALL PROCESSOR USER S MANUAL MOTOROLA ...

Page 26: ...nfigure operation of the following functions Access permission of internal peripheral registers Address space of internal peripheral registers Bus timeout control and status bus error generator The on chip peripherals occupy a reserved 4096 byte block of address space for their registers This block is located at FFFFF000 and FFF000 from reset There is a double map control bit in the SCR to disable...

Page 27: ...s a set of 16 general purpose programmable chip select signals arranged as 4 groups of 4 that includes two special purpose chip select signals Each of the general purpose signals can address an entire 32 bit address range and has a common set of features The CSA0 is special in the sense that it is also a boot device chip select From reset all the addresses are mapped to device CSA0 until the group...

Page 28: ...s 2 whether a DTACK is automatically generated for this chip select and 3 the number of wait states from zero to six 2 1 2 1 PROGRAMMABLE DATA BUS SIZE Each of the chip selects includes the facility of a data bus port sizing extension to the basic M68000 bus This allows the system designer to mix 16 bit and 8 bit contiguous address memory devices RAM ROM on a 16 bit data bus system If the CPU core...

Page 29: ...old reset to assert in response to any address except the on chip module register space i e FFFFF000 to FFFFFFFF or FFF000 to FFFFFF This ensures a chip select to the boot ROM or EPROM to fetch the reset vector and execute the initialization code which should set up the SCR and the chip select ranges early on in that initialization sequence The data bus port size for CSA0 on reset and hence the da...

Page 30: ...2 PROGRAMMING MODEL The various modules in the MC68328 processor including the SIM28 contain registers that control the modules and provide status information from the modules All of these registers reside in the top 4096 byte range FFFFF000 to FFFFFFFF of addresses in the memory map of the MC68EC000 core processor It is also doubly mapped at FFF000 to FFFFFF from reset 2 2 1 System Control Regist...

Page 31: ...t limits the on chip register accesses to supervisor only Writing a 1 to this location sets to supervisor only mode Clearing this bit allows both su pervisor and user to access the on chip registers DMAP Double Map If this bit is set the register is mapped at FFFFF000 FFFFFFFF and FFF000 FFFFFF If the bit is cleared the register is mapped at FFFFF000 FFFFFFFF only This bit is set to 1 after reset ...

Page 32: ...nal interrupt level 3 IRQ2 external interrupt level 2 IRQ1 external interrupt level1 Users have access to the upper five bits of the vector that allow placement of the interrupt vector table anywhere in the vector space The interrupt controller gathers prioritizes and posts interrupts to the M68000 core Full compatibility with normal M68000 operation is maintained Here s a typical scenario when an...

Page 33: ...masked its status is accessible in the interrupt pending register 2 3 2 Programmer s Model This section describes the bits and registers that control the interrupt module All unused bits may be written with no effect When they are read they indicate 0 2 3 2 1 INTERRUPT VECTOR REGISTER IVR This register programs the upper 5 bits of the interrupt vector During the interrupt acknowledge cycle the low...

Page 34: ...ce of the interrupt On re set this bit is cleared to 0 level sensitive interrupt 0 Level sensitive interrupt 1 Edge sensitive interrupt ET3 IRQ3 Edge Trigger Select While this bit is set the external IRQ3 bit is an edge triggered interrupt Users must clear IRQ3 in the interrupt status register to clear the interrupt While this bit is low IRQ3 is a level sensitive interrupt In this case users must ...

Page 35: ... The interrupt mask bit positions corresponds to the bits in the interrupt status register inter rupt pending register and wakeup enable register When each bit is set its interrupt is masked disabled MSPIM Mask SPI Master Interrupt Bit 0 This bit while set indicates that the SPI master interrupt is masked It is set to 1 after re set 0 Enable SPI master interrupt 1 Mask SPI master interrupt MTMR2 M...

Page 36: ...set to 1 after reset 0 Enable PWM interrupt 1 Mask PWM interrupt MINT0 Mask External INT0 Bit 8 This bit while set indicates that the external interrupt INT0 is masked It is set to 1 after reset 0 Enable INT0 interrupt 1 Mask INT0 interrupt MINT1 Mask External INT1 Bit 9 This bit while set indicates that the external interrupt INT1 is masked It is set to 1 after reset 0 Enable INT1 interrupt 1 Mas...

Page 37: ...able INT6 interrupt 1 Mask INT6 interrupt MINT7 Mask External INT7 Bit 15 This bit while set indicates that the external interrupt INT7 is masked It is set to 1 after reset 0 Enable INT7 interrupt 1 Mask INT7 interrupt MIRQ1 Mask IRQ1 Interrupt Bit 16 This bit while set indicates that the external IRQ level 1 interrupt is masked It is set to 1 after reset 0 Enable IRQ1 interrupt 1 Mask IRQ1 interr...

Page 38: ...sense that if the interrupt level is masked all the way to level 7 in the M68000 core the IRQ7 interrupt is still observed by the processor because the level 7 interrupt is nonmaskable for the M68000 core It can however be masked by this control bit 0 Enable IRQ7 interrupt 1 Mask IRQ7 interrupt 2 3 2 5 INTERRUPT WAKEUP ENABLE REGISTER IWR This control register enables the corresponding interrupt s...

Page 39: ...ing a 0 to this bit and the other bits of this register has no effect 0 No level 6 interrupt pending 1 Level 6 interrupt pending UART This bit while set indicates that the UART module needs service The transmitter might need data the receiver might have data ready to transfer to memory or the CTS or GPIO pins might have changed state Each of these interrupts is maskable in the UART control registe...

Page 40: ...be a level sensitive interrupt users must clear the source of the interrupt If IRQ2 is set to be an edge sensitive interrupt users must clear the interrupt by writing a 1 to this status bit Writing a 0 to this bit and the remainder of the bits in this register has no effect 0 No Level 2 interrupt pending 1 Level 2 interrupt pending IRQ1 This bit while set indicates that an external device requests...

Page 41: ...until the register is initialized and the valid bit is set in the corresponding group base address registers The only exception is the CSA0 which is the boot device chip select 2 5 1 Group Base Address Registers GBR0 GBR3 There are four 16 bit group base address registers in the chip select function one for each chip select group The group registers group base address register and group base addre...

Page 42: ...group base address register In this case the group has a 1 Mbyte space If bit 4 GMA20 bit is set and the remainder of the bits are clear the group is selected if A31 to A21 are the same as the value programmed in the group base address register This provides 2 Mbyte of space for the group Further decoding is per formed for each chip select by comparing lower address lines and the chip select regis...

Page 43: ...esponding bit ADDRESS COMPARE 23 12 Group C D This bit field is the address compare field A group address match and a match of address bits 23 12 generate this chip select ADDRESS MASK 23 12 This field masks corresponding bits in the address compare field A 1 forces a true com parison don t care on the corresponding bit BSW Bus Width This bit sets the bus width for this chip select area 0 8 bit 1 ...

Page 44: ... 101 Five wait states 110 Six wait states 111 External DTACK 2 6 PCMCIA 1 0 SUPPORT The MC68328 processor supports PCMCIA 1 0 memory card chip selects and read write signals To meet the fanout requirement use external buffers to interface to the memory card 2 6 1 Block Diagram Overview Figure 2 13 PCMCIA Block Diagram The PCMCIA address decode is through CSD3 Selecting CSD3 assets the correspondin...

Page 45: ...System Integration Module 2 20 MC68328 DRAGONBALL PROCESSOR USER S MANUAL MOTOROLA ...

Page 46: ... clock can be divided to provide a system clock as low as 1 16th of the voltage controlled oscillator VCO frequency The low frequency reference clock 32 768 kHz or 38 4 kHz is always available to the real time clock or timer The PLL can be disabled to save power but it can be re enabled within 2 ms of a wake up interrupt This block in conjunction with the power control block provides an efficient ...

Page 47: ... VCO 16 1XX VCO 1 binary 100 after reset These bits can be changed at any time The VCO frequency is unaffected by changes CLKEN This bit enables the CLKO pin while high 1 CLKO enabled 0 CLKO disabled DISPLL Disable PLL This bit while high disables the PLL The system clock is shut down and the MC68328 processor assumes its lowest power state Only the 32 kHz clock runs Refer to Section 3 4 3 for a d...

Page 48: ...egins oscillation within several hundred millisec onds While reset remains asserted the PLL begins the lockup sequence and locks within several milliseconds of the crystal oscillator startup Once lockup occurs the system clock is available at the default master frequency of 16 580608 MHz assuming a 32 768 kHz crys tal To generate the master frequency multiply the reference 32 768 kHz by the PLL di...

Page 49: ...ible frequency SYSCLK SEL 7 FREQSEL is the address of the frequency select register NEWFREQ is the new frequency value P and Q values to be programmed lea FFF202 A0 point to the Freq Sel Register move w NEWFREQ D1 prepare the new frequency Q and P WAIT move w A0 D0 get the contents of the register bpl w WAIT wait for CLK32 to go high move w D1 A0 load the new frequency WAIT1 move w A0 D0 the progr...

Page 50: ...ed or bursted with a low duty cycle When a wakeup interrupt occurs the clock is immediately enabled allowing the CPU to service the request The DMA controller is not affected by the power controller It has full access to the bus while the CPU is idle keeping the screen refreshed The following sections describe the use and operation of the power control block 3 4 1 Description Figure 3 4 is a block...

Page 51: ...hen a wakeup event occurs the clock immediately restarts so the processor can service the wakeup event interrupt The power controller burst period is 31 CLK32 periods or approximately 1 msec Note that the LCD DMA controller has access to the bus at all times and the SYSCLK master clock to all peripherals is continuously active Figure 3 4 Power Control Module Figure 3 5 Power Control Operation MPU ...

Page 52: ...lock bursts This bit immediately enters the power save mode without waiting for the power controller to cycle through a complete burst period This bit disables the CPU clock after the bus cy cle that follows the next CLK32 rising edge When the system is to enter the doze mode this bit is set On the next burst period or interrupt the clock will restart for its allotted pe riod This bit is reset to ...

Page 53: ...he MC68EC000 If an interrupt is received the power controller is automatically disabled It is up to the interrupt service routine to re enable the power controller 3 4 3 2 DOZE OPERATION The MC68EC000 clock can be disabled for extended periods by setting the WIDTH register to 00000 The MC68EC000 clock is enabled when it receives an interrupt At the end of the service routine the power controller c...

Page 54: ... soft horizontal scrolling The LCDC fetches display data directly from system memory through periodic DMA transfer cycles The bus bandwidth used by the LCDC is low thereby enabling the MC68EC000 core to have sufficient computing bandwidth for other tasks 4 1 LCDC SYSTEM OVERVIEW The LCDC is built of six basic blocks namely MPU interface registers screen DMA control ler line buffer cursor logic fra...

Page 55: ... generate up to 4 gray levels from the choice of 7 density levels 0 1 4 5 16 1 2 11 16 3 4 1 as in Table 4 3 The density level corresponds to the number of times the pixel is being turned on when the display is refreshed frame by frame Because the crystal formulations and driving volt age may vary the visual gray quality can be tuned by programming the gray palette map ping register GPMR to obtain...

Page 56: ...ogram the output pixel data to be negated See the POLCF register description for details First Line Marker LFLM This signal indicates the start of a new display frame The LFLM signal becomes active after the first line pulse of the frame and remains active until the next line pulse at which point it de asserts and remains inactive until the next frame Users can program the LFLM signal using softwa...

Page 57: ... The LCDC signal continuously pumps the pixel data into the LCD panel via the LCD data bus The bus is timed by shift clock LSCLK line pulse LLP and first line marker LFLM The LSCLK clocks the pixel data into the display drivers internal shift register The LP latches the shifted pixel data into a wide latch at the end of a line while the LFLM marks the first line of the displayed page The LCDC sign...

Page 58: ...vely The LLP and LFLM timing are similar for all panel modes supported by LCDC In additional to the interface timing pins discussed above an alternate crystal direction LACD pin in LCDC will toggle after a pre programmed number of LFLM pulses This pin prevents crystal degradation in the LCD panel ...

Page 59: ...E 1 1 2 3 m 2 m 2 1 79 80 b 2 Bit LCD Data Bus PBSIZ 01 LD0 0 0 0 4 0 8 LD1 0 1 0 5 0 9 LD2 0 2 0 6 0 10 LD3 0 3 0 7 0 11 0 m 8 0 m 4 0 m 7 0 m 3 0 m 6 0 m 2 0 m 5 0 m 1 0 152 0 156 0 153 0 157 0 154 0 158 0 155 0 159 SCK 1 2 3 m 4 m 4 1 39 40 LP FLM LP LINE 1 LINE 2 LINE 3 LINE 4 LINE n LINE 1 a 4 Bit LCD Data Bus PBSIZ 10 SCLK LD0 0 0 0 1 0 2 LP FLM 0 m 2 0 m 1 LP LINE 1 0 78 0 79 LINE 2 LINE 3 ...

Page 60: ... units are measured in pixel counts in this figure Figure 4 4 LCD Screen Format The screen width XMAX and screen height YMAX registers specify the LCD panel size The LCD will start scanning the display memory at the location pointed to by the screen starting address SSA register Therefore the LCD panel will display the shaded area in Figure 4 4 The virtual page width VPW and virtual page height VP...

Page 61: ...ntrol circuitry inside the LCDC will generate intermediate gray tones on the LCD panel by adjusting the densities of 1 s and 0 s over many frames A maximum of 4 gray levels can be simultaneously displayed on the LCD screen The system memory data in both 1 and 2 bit per pixel modes are mapped as shown in Fig ure 4 5 4 5 4 Gray Scale Generation The LCDC is configured to drive only a single screen mo...

Page 62: ...6 0 7 0 X 8 Y 1 X 7 Y 1 X 6 Y 1 X 5 Y 1 X 4 Y 1 X 3 Y 1 X 2 Y 1 X 1 Y 1 1 Bit Per Pixel Mode Byte oriented for clarity LCD Drivers LCD Drivers 1 0 2 0 X 1 0 0 0 0 Y 1 1 Y 1 2 Y 1 X 1 Y 1 Byte oriented for clarity System ROM RAM System ROM RAM Display Mapping 2 Bits Per Pixel Mode 7 6 5 4 3 2 1 0 0 0 1 0 2 0 3 0 X 4 Y 1 X 3 Y 1 X 2 Y 1 X 1 Y 1 Display Mapping ...

Page 63: ...the LCDON bit 2 Delay for 1 2ms 3 Turn on the VLCD by I O driving a transistor When setting the LCDON bit register CKCON bit 7 to 1 LCDC itself will enter a low power mode by stopping its own pixel clock prior to the next line buffer fill DMA Additional screen DMA and display refresh operations will then be stopped in this mode When the LCDC is switched back on DMA and screen refresh activities wi...

Page 64: ...l get control of the bus signal and issue 8 or 16 word reads see setting of CKCON register from memory The read data is then passed to the next stage internally to generate the LCD timing flyby During the LCD access cycles out put enable and chip select signals for the corresponding system SRAM chip will be asserted by the chip select logic inside the SIM The minimum bus bandwidth obstruct can be ...

Page 65: ...LCD Controller 4 12 MC68328 DRAGONBALL PROCESSOR USER S MANUAL MOTOROLA Figure 4 7 One Clock per DMA Transfer 0 Wait State SYSCLK BR ADDRESS BG DATA OE CS ...

Page 66: ...ual page width in pixels divided by c where c is 16 for black and white display and 8 for gray level 4 7 2 Screen Format Registers 4 7 2 1 SCREEN WIDTH REGISTER XMAX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SSA31 SSA30 SSA29 SSA28 SSA27 SSA26 SSA25 SSA24 SSA23 SSA22 SSA21 SSA20 SSA19 SSA18 SSA17 SSA16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSA15 SSA14 SSA13 SSA12 SSA11 SSA10 SSA9 SSA8 SSA7 S...

Page 67: ...is disabled 01 Full density black cursor 10 Reversed video 11 Do not use CXP9 CXP0 Cursor s horizontal starting position X in pixel count from 0 to XMAX 4 7 3 2 CURSOR Y POSITION REGISTER CYP CYP8 CYP0 Cursor s vertical starting position Y in pixel count from 0 to YMAX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UNUSED YM9 YM8 YM7 YM6 YM5 YM4 YM3 YM2 YM1 YM0 Address FF FFFA0A Reset Value 01FF Figure 4 1...

Page 68: ... 0 Blink disable BD6 BD0 Blink divisor The cursor will toggle once per specified number of internal frame pulses plus one The half period may be as long as 2 seconds 4 7 4 LCD Panel Interface Registers 4 7 4 1 PANEL INTERFACE CONFIGURATION REGISTER PICF PBSIZ1 PBSIZ0 Panel Bus Width LCD panel bus size 00 1 bit 01 2 bit 10 4 bit 11 unused 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UNUSED CW4 CW3 CW2 CW1...

Page 69: ...OLARITY CONFIGURATION REGISTER POLCF LCKPOL LCD Shift Clock Polarity This bit controls the polarity of the LCD shift clock active edge 0 Active negative edge of LCLK 1 Active positive edge of LCLK FLMPOL First line marker polarity 0 Active High 1 Active Low LPPOL Line pulse polarity 0 Active high 1 Active low PIXPOL Pixel polarity 0 Active high 1 Active low 7 6 5 4 3 2 1 0 UNUSED LCKPOL FLMPOL LPP...

Page 70: ...1 63 will yield N 2 to 64 If set to 0 N 1 the PIX clock will be used di rectly bypassing the divider circuit Input source is selected by PCDS in CKCON register 4 7 5 2 CLOCKING CONTROL REGISTER CKCON LCDCON This bit controls the LCDC block 0 Disable LCDC 1 Enable LCDC NOTE The internal LCDC logic will be switched off in step with the FLM pulse DMA16 This bit controls the length of the DMA burst 0 ...

Page 71: ...ds required to fill one line on the display panel The count is typically equal to the screen width in pixels divided by 16 for black and white display or by 8 if in gray scale For panning add one more count for black and white and two for gray display 4 7 5 4 OCTET TERMINAL COUNT REGISTER OTCR OTC8 OTC1 Controls the time interval between two lines therefore the frame refresh rate can also be finel...

Page 72: ...egisters 4 7 6 1 FRAME RATE MODULATION CONTROL REGISTER FRCM XMOD YMOD Frame Rate Modulation Control These numbers modulate adjacent pixels at different time periods to avoid spatial flicker or jitter when using FRC These values must be optimized by manually fine tuning the tar get LCD panel See Section 4 5 5 Gray Palette Mapping for details 4 7 6 2 GRAY PALETTE MAPPING REGISTER GPMR GMN Gray pale...

Page 73: ... overhead to the data bus Consider a typical case scenario Screen size 320 x 240 pixels Bits per pixel 2 bits pixel Screen refresh rate 60 Hz System clock 16 67 MHz Host bus size 16 bit DMA access cycle 2 cycles per 16 bit word The period Tl that LCDC must update one line of the screen is EQ 1 At the same period the line buffer must be filled The duration TDMA which the DMA cycle will take up the ...

Page 74: ... of 3 groups that are toggled by a 1 Hz clock The seconds and minutes counters are 6 bits long while the hours counter is 5 bits long The time counters offer seconds minutes and hours data in 24 hour format The prescaler stages are tapped to support several features Periodic interrupts at 1 Hz and 1 minute are available as well as an interrupt at the midnight rollover of the hours counter 5 1 2 Al...

Page 75: ... new values Unused bits read 0 HOURS These 5 bits when read indicate the current hour and can be set to any value between 0 and 23 Figure 5 1 Real Time Clock 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Unused HOURS Unused MINUTES 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused SECONDS Address FF FFFB00 Reset Value 00000000 Figure 5 2 Hours Minutes Seconds Register PRESCALER SECOND MINUTE HOUR ALA...

Page 76: ...hese 6 bits when read indicate the current setting of the alarm s minute and can be set to any value between 0 and 59 SECONDS These 6 bits when read indicate the current setting of the alarm s second and can be set to any value between 0 and 59 5 1 4 3 RTC CONTROL REGISTER RTCCTL Figure 5 4 Control Register ENABLE RTC Enable This bit enables the RTC 1 Enable RTC 0 Disable RTC 38 4 38 4 kHz Referen...

Page 77: ...0 No 1 Hz interrupt occurred DAY FLAG If enabled this bit is set for every 24 hour clock increment at midnight and an interrupt posted 1 24 hour rollover interrupt occurred 0 No 24 hour rollover interrupt ALARM FLAG If enabled an alarm flag is set on a compare match between the RTC and the alarm reg ister value Note the alarm will recur every 24 hours If a single alarm is required clear the interr...

Page 78: ...enabled 0 24 hour interrupt disabled ALARM INTERRUPT ENABLE This bit enables the alarm interrupt 1 Alarm interrupt enabled 0 Alarm interrupt disabled MIN INT ENABLE This bit enables the minute tick interrupt 1 Minute tick interrupt enables 0 Minute tick interrupt disabled SW INTERRUPT ENABLE This bit enables the stopwatch interrupt The stopwatch counts down and remains at dec imal 1 until it is re...

Page 79: ...unused bits read 0 STOPWATCH COUNT This field contains the stopwatch countdown value The highest allowable value is 62 min utes The countdown will not be activated again until a nonzero value less than 63 min utes is written to the stopwatch count register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UNUSED STOPWATCH COUNT ADDRESS FF FFFB12 Reset Value 0000 ...

Page 80: ...clock input including external clock Input capture capability with programmable trigger edge on input pins Output compare with programmable mode for the output pins Cascading timers for constructing one 32 bit timer Free run and restart modes The software watchdog timer has the following features 16 bit counter and reference register Maximum period of 16 38 seconds Figure 6 1 Timer Block Diagram C...

Page 81: ...nce value the corresponding timer status register TSR bit is set and an interrupt is issued if the interrupt enable bit in TCR is set Each timer may output a signal on the timer output TOUT1 or TOUT2 pin when it reaches the reference value as selected by the output mode OM bit of the corresponding control register TCR This signal can be an active low pulse for a system clock wide or a toggle of th...

Page 82: ...ol status register The counter is locked after it starts running it will be disabled and cleared if and only if a software reset or external reset is asserted Once the count reaches the ref erence value programmed in the reference register either a maskable interrupt or a soft ware reset will be issued to the system depending on the FI bit in the control status register The counter asserts an inte...

Page 83: ... and generate interrupt on capture 10 Capture on falling edge and generate interrupt on capture 11 Capture on rising or falling edges and generate interrupt on capture OM Output Mode This bit controls the output mode of the timer after a reference compare event 0 Active low pulse for one SYSCLK period 1 Toggle output IRQEN Reference Event Interrupt Enable This bit controls the generation of an int...

Page 84: ...Enable This bit enables the timer module 0 Timer disabled 1 Timer enabled NOTE When this bit transitions from 0 to 1 the counter is reset to 0000 The other registers are not disturbed 6 4 1 3 TIMER PRESCALER REGISTER These identical registers control the overall indi vidual timer operation PRESCALER These bits determine the divide value of the prescaler between 1 and 256 00 divides by 1 and FF div...

Page 85: ... if enabled These bits are cleared by writing 00 and will clear only if they have been read while set which ensures that an interrupt will not be missed if it occurs between the status read and the interrupt clear CAPT Capture Event While high this bit indicates that a capture event occurred 0 No capture event occurred 1 Capture event occurred COMP Compare Event While high this bit indicates that ...

Page 86: ...EGISTER The watchdog counter register is a 16 bit up counter and appears as a memory mapped register that may be read at any time Figure 6 10 Watchdog Counter Register COUNT This is the current count value A read cycle to the counter register causes the current value of the watchdog timer to be read Reading the watchdog timer does not affect the counting operation A write cycle to the counter regi...

Page 87: ...g is disabled 0 Watchdog disabled 1 Watchdog enabled FI This bit indicates that the interrupt should be generated instead of a software reset 0 Software reset mode the watchdog interrupt is disabled 1 Forced watchdog interrupt instead of software reset LOCK This bit is not user programmable It is set when the watchdog timer is activated 0 Watchdog timer is not locked 1 Watchdog timer is locked dis...

Page 88: ...ration Basic ports multiplex two functions onto one pin One function is the I O and the other is the internal module connected to this pin Figure 7 1 refers to signals to and from a module For example for port K bit 0 the Data from module signal is connected to the master SPI mod ule TXD signal Because this bit is output only the Output Enable from module signal is always asserted enabling the out...

Page 89: ...mode 1 s bits 5 3 in slave SPI mode 0 s bits 2 0 in I O mode 1 s Value in port K DIRECTION register C0 bits 7 6 outputs 1 s bits 5 3 are inputs 0 s see Note below bits 2 0 inputs 0 s Value in port K DATA register bits 7 6 are written with the value to be output on port K bits 7 6 bits 5 3 when read contain the current value on the slave SPI pins bits 2 0 contain current value on port K bits 2 0 Bi...

Page 90: ...n 2 3 for more information Individual interrupts can be configured as edge or level sensitive and the polarity can be selected 7 1 2 Port A Port A is multiplexed with address lines A16 A23 Unused address pins can serve as parallel I Os on a bit by bit basis After reset these signals default to their address function Three Figure 7 2 Pullup Port Figure 7 3 Interrupt Port 0 1 SEL 0 1 SEL SELECT DIRE...

Page 91: ...r they are configured as input or output These bits reset to 0 while the SELECT bits are low SELECT SEL 7 0 These bits select whether address 23 16 or I O port signals are connected to the pins While high the port I O functions are connected to the pin While low the address function is connected 7 1 3 Port B Port B is multiplexed with data lines D7 D0 In an 8 bit only system these pins can be con ...

Page 92: ...byte or I O port signals are connected to the pins While high the port I O function is connected to the pin While low the D7 D0 func tions are connected 7 1 4 Port C Port C is multiplexed with various 68000 bus control signals that are identified below All 8 bits are implemented in the registers but only 6 bits connect to the outside As with other ports each bit can be individually configured Bit ...

Page 93: ...ss pins are connected 7 1 5 Port D Port D has features intended for use as a keyboard input port however it can be used as a general purpose port Multiple keyboard support functions are provided As with the other ports each pin can be configured as an input or output on a bit by bit basis While config ured as inputs each pin can generate a CPU interrupt Additionally a group interrupt can be genera...

Page 94: ... enable the pullup resistors on the port While high the pullup resistors are en abled While low the pullup resistors are disabled The pullups are enabled on reset POLARITY POL 7 0 These bits select the input signal polarity While high the input data is inverted before be ing presented to the holding register while low the data is unchanged Interrupts are ac tive high or rising edge while these bit...

Page 95: ...ts are high output D 7 0 controls the data to the pins While the DIRECTION bits are low input D 7 0 reports the signal level on the pins The data bits may be written at any time Bits that are configured as inputs will accept the data but the written data will not be accessible until their respective pins are configured as out Table 7 2 Port E Bit Functions Bit Port Function Other Function 0 none n...

Page 96: ...IR 7 0 These bits control the pin directions While high the pins are outputs while low the pins are inputs These bits reset to 0 and have no function while the select bits are low DATA D 7 0 These bits control or report the data on the pins while the associated SELECT bits are high While the DIRECTION bits are high D 7 0 controls the data to the pins While the DIRECTION bits are low D 7 0 reports ...

Page 97: ...ls are identified below Refer to the timer PWM RTC and UART sections for descriptions of signal func tions All 8 bits are implemented in the registers and each is connected to the outside As with other ports each bit can be individually configured as needed The programmer s model for port G is shown below Table 7 3 Port G Bit Functions Bit Port Function Other Function 0 Bit 0 UART TXD 1 Bit 1 UART...

Page 98: ...ible until the respective pins are configured as outputs Note that the actual value on the pin is reported when these bits are read Note While PC0MOCLK is high the RTCOUT bit is disabled and be comes an input for the 32 KHz real time clock reference PULLUP PU 7 0 These bits enable the pullup resistors on the port While high the pullup resistors are en abled while low they are disabled Port E bit 7...

Page 99: ...ata bits may be written at any time Bits that are configured as inputs will accept the written data but it will not be accessible until the respective pins are configured as outputs The actual value on the pin is reported when these bits are read SELECT SEL 7 0 These bits select whether chip select or port I O signals are connected to the pins While high the port I O function is connected to the p...

Page 100: ...re low the levels on the pins are reported These bits reset to 0 while the SELECT bits are low The data bits may be written at any time Bits that are configured as inputs will accept the written data but it will not be accessible until the respective pins Table 7 5 Port K Bit Functions Bit Port Function Other Function 0 Bit 0 SPIM TXD 1 Bit 1 SPIM RXD 2 Bit 2 SPIM CLKO 3 Bit 3 SPIS EN 4 Bit 4 SPIS...

Page 101: ...ch bit has a selectable pullup resistor associated with it All 8 bits are implemented in the registers and each is connected to the outside As with other ports each bit can be individually configured as needed Note that there is no alter nate signal associated with bit 7 The programmer s model for port M is shown below Table 7 6 Port M Bit Functions Bit Port Function Other Function 0 Bit 0 CTS 1 B...

Page 102: ...o 0 while the SELECT bits are low The data bits may be written at any time Bits that are configured as inputs will accept the written data but it will not be accessible until the respective pins are con figured as outputs The actual value on the pin is reported when these bits are read SELECT 7 0 These bits select whether interrupt or port I O signals are connected to the pins While high the port ...

Page 103: ...Parallel Ports 7 16 MC68328 DRAGONBALL PROCESSOR USER S MANUAL MOTOROLA ...

Page 104: ... generator Flexible clocking options Standard baud rates 300bps to 115 2kbps with 16x sample clock External 1x clock for high speed synchronous communication Programmer s model optimized for 16 bit bus 8 maskable interrupts Low power idle mode The UART performs all normal operations associated with start stop asynchronous commu nication Serial data is transmitted and received at standard bit rates...

Page 105: ...in is the receiver serial input While in normal operation NRZ data is expected While in IrDA mode a narrow pulse is expected for each 0 bit received Use external cir cuitry to convert the infrared signal to an electrical signal RS 232 applications need an external RS 232 receiver to convert from RS 232 voltage levels RTS Ready To Send This output pin serves two purposes Normally the receiver indic...

Page 106: ...e When a character is available for transmission the start stop and parity if enabled bits are added to the character and it is serially shifted at the selected bit rate The transmit ter posts a maskable interrupt when it needs parallel data Three interrupts are available If users want to take full advantage of the 8 byte FIFO the FIFO EMPTY interrupt should be enabled In the interrupt service rou...

Page 107: ...pt is used This interrupt is generated when 4 bytes have been entered into the FIFO If the FIFO is not needed the DATA READY interrupt is used This interrupt is generated whenever one or more characters are present in the FIFO While the IrDA interface is enabled the receiver expects narrow pulses for each 0 bit received otherwise normal NRZ is expected An IrDA transceiver external to the MC68328 p...

Page 108: ...e FIFO is flushed This bit resets to 0 0 Receiver disabled and receive FIFO flushed 1 Receiver enabled TX ENABLE This bit enables the transmitter block While this bit is low the transmitter is disabled and the transmit FIFO is flushed This bit resets to 0 0 Transmitter disabled and transmit FIFO flushed 1 Transmitter enabled RX CLK CONT Receiver Clock Control This bit controls the receiver operati...

Page 109: ...bits transmitted 8 7 This bit controls the character length While high the transmitter and receiver are in 8 bit mode While low they are in 7 bit mode The transmitter then ignores B7 and the receiver sets B7 to 0 0 7 bit transmit and receive character length 1 8 bit transmit and receive character length GPIO DELTA ENABLE This bit enables an interrupt when the GPIO pin while configured as an input ...

Page 110: ...PTY interrupt enabled TX HALF ENABLE While high this bit enables an interrupt when the transmit FIFO is less than half full While this bit is low the TX HALF interrupt is disabled This bit resets to 0 0 TX HALF interrupt disabled 1 TX HALF interrupt enabled TX AVAIL ENABLE Transmitter Available For New Data While high this bit enables an interrupt when the transmitter has a slot available in the F...

Page 111: ...he direction of the GPIO pin While this bit is high the pin is an input While this bit is low GPIO is an output 0 GPIO is input 1 GPIO is output GPIO SRC This bit controls the source of the GPIO pin While high the source is the 1x clock from the baud rate generator While low the source is the GPIO bit While the GPIO DIR bit is 0 this bit has no function 0 GPIO driven by GPIO bit 1 GPIO driven by b...

Page 112: ...ly bit indicates that the receiver FIFO is more than half full 0 Receive FIFO less than half full no interrupt posted 1 Receive FIFO more than half full interrupt posted DATA READY This read only bit indicates that at least one byte is present in the receive FIFO 0 No data in receive FIFO 1 Data in receive FIFO OVRUN FIFO Overrun While high this read only bit indicates that the receiver overwrote ...

Page 113: ...nly bit indicates that the current character was detected with a par ity error indicating the possibility of corrupted data This bit is updated for each character read from the FIFO While parity is disabled this bit always reads zero DATA These read only bits are the next receive character in the FIFO These bits have no mean ing if the DATA READY bit is 0 While in 7 bit mode the MSB is forced to 0...

Page 114: ...while high forces the CTS signal presented to the transmitter to always be as serted effectively ignoring the external pin While in this mode the CTS pin can serve as a general purpose input 0 Transmit only while CTS pin is asserted 1 Ignore CTS pin CTS STATUS This bit indicates the current status of the CTS pin A snapshot of the pin is taken imme diately before this bit is presented to the data b...

Page 115: ...ded by the external system 0 Bit clock generated by baud generator 1 Bit clock supplied from GPIO input FORCE PERR While high this bit forces the transmitter to generate parity errors if parity is enabled This bit is provided for system debugging 0 Generate normal parity 1 Generate inverted parity error LOOP This bit controls loopback for system test purposes While this bit is high the receiver in...

Page 116: ... pin is 1 1 RTS pin is 0 IRDA ENABLE This bit enables the IrDA interface 0 Normal NRZ operation 1 IRDA operation LOOP IR This bit controls a loopback from transmitter to receiver in the IrDA interface This bit is provided for system testing 0 No IR loop 1 Connect IR transmit to IR receiver UNUSED These bits are unused and read 0 ...

Page 117: ...UART 8 14 MC68328 DRAGONBALL PROCESSOR USER S MANUAL MOTOROLA ...

Page 118: ... slave SPI 9 2 OPERATION Users first initialize the SPIS program register The SPIS then waits for the input enable SPSEN and clock SPSCLK to control the data transfer The shift register fills with data over the next 8 clock cycles On the eighth clock the shift register contents loads into the data buffer The SPISIRQ bit is set posting an interrupt The valid data in the buffer awaits the service ro...

Page 119: ... in on each leading edge of SPSCLK while in normal mode POL 0 or on each trailing edge of SPSCLK in polarity inverted mode POL 1 This signal pin is multiplexed with other signals to port K bit 4 Refer to Section 7 1 10 for more details SPSCLK This pin is the shift clock input SPSEN This pin indicates that an SPI transfer is in progress After the enable becomes active the SPIS state machine respond...

Page 120: ... is initially set to 0 0 SPSEN is active low 1 SPSEN is active high DATARDY Data Ready This flag indicates that the data buffer contains updated data The DATARDY flag is au tomatically cleared after the data is read 0 Buffer is empty 1 Buffer has data OVRWR Overwrite This bit indicates that the data buffer was overwritten An interrupt is posted when an over write occurs The OVRWR flag is automatic...

Page 121: ...s high idle 1 SPISEN This status bit enables the slave SPI module 1 SPIS module enabled 0 SPIS module disabled default DATA These are the data bits shifted from the external device At every 8th SPSCLK edge data from the peripheral is loaded into this buffered register If the data buffer is not accessed before the next byte is received it will be overwritten and the OVRWR bit will be set post ing a...

Page 122: ...ps 10 1 OVERVIEW The SPIM transfers data between the MC68328 processor and peripheral devices in bursts over a serial link Enable and clock signals control the exchange data between the two devices If the external device is a talk only device the SPIM output port can be ignored and used for other purposes Figure 10 1 is a block diagram of the SPIM 10 2 OPERATION 10 2 1 Operation within SPIM module...

Page 123: ...ansfer may be programmed in phase and in polarity Figure 10 2 In phase 0 operation output data changes on falling clock edges while input data is shifted on rising edges In a phase 1 operation output data changes on rising edges of the clock and is shifted on falling edges Polarity 1 inverts the data clock relationships This flexibility allows operation with most serial peripheral devices on the m...

Page 124: ...e SPIM operation and report its status The data register exchanges data with external slave devices After reset all bits are set to 0000 10 4 1 SPIM Control Status Register This register controls the SPIM operation and reports its status DATA RATE These bits select the baud rate of the SPMCLK based of divisions of the system clock The master clock for the SPIM is SYSCLK The bits are encoded as 000...

Page 125: ...the incoming SPIM interrupt by masking it in the IMR in the interrupt controller SPIMIRQ An interrupt is asserted at the end of an exchange assuming IRQEN is enabled This bit is asserted until users clear it by writing a 0 Users can write these bits to generate an IRQ on demand 0 No interrupt posted 1 Interrupt posted IRQEN This bit will enable the SPIM interrupt This bit is cleared to 0 on reset ...

Page 126: ...ta if they are read while the XCH bit is set A write to these bits will be ignored while the XCH bit is set As data is shifted MSB first outgoing data is automatically MSB justified For example if the exchange length is 10 bits the MSB of the outgoing data is bit 9 The first bit presented to the exter nal slave device will be bit 9 followed by the remaining 9 bits NOTE Users should reload the data...

Page 127: ...SPI Master 10 6 MC68328 DRAGONBALL PROCESSOR USER S MANUAL MOTOROLA ...

Page 128: ...ample values to the PWM into the width register and pro vides a low pass filter on the output It also provides a high quality digitally generated sound source The selected period determines the reconstruction rate Typically for voice quality the rate will be between 6 kHz and 8 kHz The following figure relates the pulse stream to the filtered audio output The width and period registers are double ...

Page 129: ...this bit to im mediately post a PWM interrupt for debugging purposes This bit automatically clears it self after it is read while set eliminating an extra write cycle in the interrupt service routine If the IRQEN bit is 0 this bit can be polled to indicate the status of the period comparator 0 No PWM period rollover 1 PWM period rolled over IRQEN This bit controls the PWM interrupt While this bit ...

Page 130: ...mpare event occurs 0 Normal polarity 1 Inverted polarity PWMEN This bit enables the PWM While disabled the PWM is in low power mode and the pres caler does not count The output pin is forced to 1 or 0 depending on the setting of the POL bit 0 PWM disabled The clock prescaler is reset and frozen The counter is reset to 0001 and frozen The contents of the width and period registers are loaded into t...

Page 131: ... This register controls the pulse width When the counter matches the value in this register the output is reset for the duration of the period Note that if the value in this register is higher than the period register the output will never be reset resulting in a 100 duty cycle WIDTH When the counter reaches the value in this register the output is reset 11 2 4 Counter This read only register is t...

Page 132: ...6 PB6 D7 PB7 D8 D9 D10 D11 GND D12 D13 D14 D15 TMS TCK LWE UWE VCC CSA0 PE1 CSA1 PE2 CSA2 PE3 CSA3 PE4 CSB0 PE5 CSB1 PE6 CSB2 PE7 CSB3 GND PJ0 CSC0 PJ1 CSC1 PJ2 CSC2 PJ3 CSC3 PJ4 CSD0 PJ5 CSD1 PJ6 CSD2 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 ...

Page 133: ... PROTRUSION ALLOWABLEDAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0 35 0 014 H 0 08 0 003 SEATING PLANE DETAIL C DETAIL B DETAIL B BASE METAL 0 08 0 003 T L M N M M S DETAIL A DETAIL A ROTATED 90 144 PL G P 144 TQFP B B1 0 790 BSC 22 00 BSC 0 866 BSC 11 00 BSC 0 433 BSC 22 00 BSC 0 866 BSC 11 00 BSC 0 433 BSC 0 790 BSC 10 00 BSC 10 00 BSC 0 25 BSC 0 010 BSC 0 394 BSC 0 394 BSC C D E...

Page 134: ...ical Specifications Chip Select Write Cycle Timing PRELIMINARY 13 4 AC ELECTRICAL SPECIFICATIONS READ AND WRITE CYCLES Frequency 0 to 16 MHz GND 0 V TA TL to TH see Figure 13 1 and Figure 13 2 Rating Symbol Value Unit Supply Voltage VCC 0 3 to 7 0 V Input Voltage Vin 0 3 to 7 0 V Maximum Operating Temperature Range TA TL to TH 0 to 70 C Storage Temperature Tstg 55 to 150 C Characteristic 3 3 V Uni...

Page 135: ...3 2 AC Electrical Specifications Chip Select Read Cycle Timing PRELIMINARY Num Characteristic 3 3 V Unit Min Max 1 Addr Valid to CSx Asserted 40 ns 2 ASx to CSx 1 20 ns 3 CSx Width Asserted 140 ns 4 CLKOUT to Addr 0 30 ns 5 CLKOUT toR W 0 30 ns 6 CLKOUT to OE 0 30 ns CLKOUT S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 SW SW S5 A0 A31 AS R W CSx D0 D15 UWE LWE CEI CE2 WE OE 2 1 3 4 6 5 5 ...

Page 136: ...RY MOTOROLA MC68328 DRAGONBALL PROCESSOR USER S MANUAL 13 3 Figure 13 2 Chip Select Read Cycle Timing when the CPU is the Bus Master PRELIMINARY CLKOUT S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 SW SW A0 A31 AS R W CSx D0 D15 OE 2 1 3 4 5 5 6 ...

Page 137: ...Electrical Characteristics PRELIMINARY MOTOROLA MC68328 DRAGONBALL PROCESSOR USER S MANUAL 13 4 ...

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