Chapter 6. Message Digest Execution Unit
6-3
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Operational Registers
Table 6-2. MCR Field Descriptions
Bits
Name
Description
0–19
—
Reserved, should be cleared.
20
ENGO
Enables automatic start of hashing as soon as the MDMB buffers have all been written. It
is not necessary to set the GO bit manually.
21
OPAD
The assertion of OPAD causes:
1. The value written to the 512 bit Message Buffer to be exclusive-ORed with the outer
hash pad value
2. Unlike IPAD, a procedural change occurs: upon starting the hash of the value written to
the Message Buffer, the contents of the Message Digest Buffer is copied to the Message
Buffer, and is padded appropriately.
By performing the copy from MDB to MB, the step of appending the inner hash result to
the padded key is performed automatically. OPAD is autocleared upon completion of a
hash of a single message block.
22
IPAD
The assertion of IPAD causes the value written to the 512 bit Message Buffer to be
exclusive-ORed with the inner hash pad value. This value is autocleared upon completion
of a hash of a single message block. Note that because this control bit affects the value
stored in the 512 bit message buffer, if block chaining is to be used, it should be set only
while the secret key is written to the 512 bit Message Buffer, and should be cleared
manually at the same time GO is asserted.
23
—
Reserved, should be cleared.
24
MD5
The assertion of the MD5 bit signifies that an MD5 hash will be computed. If both MD4
and MD5 are not asserted, a SHA-1 Hash will be computed.
25
MD4
The assertion of the MD4 bit signifies that an MD4 hash will be computed. If both MD4
and MD5 are not asserted, a SHA-1 Hash will be computed.
26
RST
The RST bit is a software reset signal. When activated, the MDEU will reset immediately,
halting any ongoing hash. All registers and buffers revert to their initial state. Normally,
asserting GO continues an existing hash function across multiple 512-bit message
blocks. Should a fresh-hash be desired for a new message block, the RST bit should be
asserted prior to loading the new message block into the Message Buffer.
27
IE
The IE bit represents the Interrupt Enable flag. When set to 1, the IRQ signal is enabled,
thus when an interrupt occurs, the IRQ signal will be activated. When the IE bit is set to 0,
all interrupts are disabled, and the IRQ output pin will be held inactive, that is, 0. The IE
bit acts as the global interrupt enable.
28
GO
The GO bit initiates the processing of the 512 bit message currently stored in the
Message Buffer. This hash will be a continuation of any existing hash of multiple
message blocks. In order to begin a new hash, the RST bit described below should be
asserted prior to loading the new 512 bit Message Block. The 512 bit Message Block is
double-buffered; a new block of message may be written while a hash is under process. If
a new block is so written, then hashing will continue with the new block without GO
needing to be reasserted.
29
BSWP
The BSWP bit causes byte-swapping of the Message Digest Buffer Registers
(MDA-MDE) as they are read out of the MDEU.
30
STEP
The STEP bit allows the MDEU to be stepped through on a single clock cycle basis.
When active, that is 1, the MDEU computes one “round” of the currently selected hash.
31
—
Reserved, should be cleared.
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Freescale Semiconductor, Inc.
For More Information On This Product,
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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