10-4
MCF5272 User’s Manual
DMA Controller Registers
10.3.2 DMA Interrupt Register (DIR)
The DIR, Figure 10-2, contains status bits and their corresponding interrupt enables.
Table 10-3 describes DIR fields.
4–2
SRCT
Source addressing type. Used internal to the MCF5272 to qualify the address bits. The value
should be compatible with the CSCRn[TM] value used for external RAM or peripheral device
access.
000 Reserved
001 User data access
010 User code access
011 Reserved
100 Reserved
101 Supervisor data access
110 Supervisor code access
111 Reserved
1–0
SRCS
Source data transfer type. Determines the amount of data the DMA controller fetches and buffers
data from the source address. When there are enough bytes to perform a destination data write of
the size programmed in DSTS, the data is written to the destination address. Thus source
accesses can be longword type and destination addresses can be line burst type. In this case, 4
longword reads are performed followed by an indivisible burst write of 4 longwords.
The most efficient data transfer method is to use longword or line burst transfer types.
SRCS
Data Transfer Type
Address Incremented by
00
Longword
4
01
Byte 1
10
Word
2
11
16-byte line burst
16. Valid only for SDRAM.
15
13
12
11
10
9
8
7
5
4
3
2
1
0
Field
—
INVEN ASCEN
—
TEEN TCEN
—
INV
ASC
—
TE
TC
Reset
0000_0000_0000_0000
R/W
R/W
Addr
MBAR + 0x00E6
Figure 10-2. DMA Interrupt Register (DIR)
Table 10-3. DIR Field Descriptions
Bits Name
Description
15–13
—
Reserved, should be cleared.
12
INVEN
Invalid combination interrupt enable.
0 INV interrupt is disabled.
1 INV interrupt is enabled.
Table 10-2. DMR Field Descriptions (Continued)
Bits
Name
Description
Summary of Contents for DigitalDNA ColdFire MCF5272
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