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Motorola CPCI-6115, Installation And Use Manual

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CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)

Transition Module Preparation and Installation

Block Diagram

90

   

5.2

Block Diagram

The block diagram for the CPCI-6115-MCPTM is shown in the following figure.

Figure 5-1

CPCI-6115-MCPTM Block Diagram

COM1

Compact

Flash 1

RS232

Transceiver

SROM

(Data)

User I/O J5 Connector

User I/O J3 Connector

IOMX Function

(Data)

Primary IDE

(Control)

16:8 Mux

10/100/1000TX 10/100/1000TX

PMC2 I/O Module

PMC1 I/O Module

REAR PANEL

Summary of Contents for CPCI-6115

Page 1: ...CPCI 6115 CompactPCI Single Board Computer Installation and Use 6806800A68D March 2008 ...

Page 2: ...the Motorola Computer Group Web site The text itself may not be published commercially in print or electronic form edited translated or otherwise altered without the permission of Motorola Inc It is possible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not available in your country Such references or in...

Page 3: ...Started 35 2 4 1 Overview of Start up Procedure 35 2 4 2 Equipment Required 36 2 5 Baseboard Preparation 36 2 5 1 Configuring the Hardware 36 2 5 2 Setting Switches and Jumpers 37 2 5 3 J6 Bus Mode Selection 38 2 5 4 J9 Standalone Operating Mode 39 2 5 5 J10 Flash Bank Selection 39 2 5 6 J15 12 V Present Header 40 2 5 7 J20 Safe Start Header 40 2 5 8 J25 SROM Initialization Enable Header 41 2 5 9 ...

Page 4: ...Header 64 3 5 13 Flash Boot Bank Select Header 64 3 5 14 Safe Start Header 65 3 5 15 Bus Mode Select Header 65 3 5 16 SROM Initialization Enable Header 65 3 5 17 Flash Bank A Write Protect Header 66 3 5 18 12 V Present Header 66 4 Functional Description 67 4 1 Overview 67 4 2 Block Diagram 68 4 3 General Description 69 4 3 1 Processor Bus Resources 69 4 3 2 Processor 70 4 3 3 L3 Cache 70 4 3 4 MV6...

Page 5: ...4 4 4 2 1 MV64360 Interrupt Controller 85 4 4 2 2 Sources of Reset 86 4 4 2 3 Machine Check 86 4 4 2 4 Soft Reset 86 4 4 2 5 SMI 86 4 4 2 6 Other Software Considerations 86 4 4 3 Onboard Power Supplies 87 4 4 4 Hot Swap Support 87 4 4 5 Hot Swap Process 87 4 4 6 Intel 21555 Hot Swap Support 87 5 Transition Module Preparation and Installation 89 5 1 Overview 89 5 2 Block Diagram 90 5 3 Preparing th...

Page 6: ... I O Module Form Factor 109 5 7 9 PMC I O Connector 110 5 7 10 Host I O Connector 110 5 7 11 PMC I O Module Presence Detection and Identification 110 5 8 Installing the PIM 111 5 9 Installing the Transition Module 113 5 10 Removing the Transition Module in a Hot Swap Chassis 114 6 Remote Start via the PCI Bus 115 6 1 Overview 115 6 2 Register Description 115 6 3 Command Response Register Descripti...

Page 7: ...y Map 127 8 2 4 Suggested PCI Memory Map 128 8 2 5 System I O Memory Map 129 8 2 6 PCI Local Bus Memory Map 129 8 2 7 CompactPCI Memory Map 129 8 2 8 Address Decoding with the 21555 130 8 2 9 L1 L2 and L3 Cache 130 8 2 10 System Memory 130 A Related Documentation 131 A 1 Embedded Communications Computing Documents 131 A 2 Manufacturers Documents 131 A 3 Related Specifications 132 ...

Page 8: ...CPCI 6115 CompactPCI Single Board Computer Installation and Use 6806800A68D Contents 6 ...

Page 9: ...ents J14 J24 62 Table 3 12 Boundary Scan JTAG Header Pin Assignments J16 63 Table 3 13 Processor JTAG COP Header Pin Assignments J17 63 Table 3 14 Stand Alone Operation Select Header Pin Assignments J9 64 Table 3 15 Flash Boot Bank Select Header Pin Assignments J10 64 Table 3 16 Safe Start ENV Header Pin Assignments J20 65 Table 3 17 Bus Mode Select Header Pin Assignments J6 65 Table 3 18 SROM Ini...

Page 10: ...signments 100 Table 5 10 COM1 COM2 Connector Pin Assignments 100 Table 5 11 Wire Interconnection List RJ 45 to DB 9 101 Table 5 12 Multiplexing Sequence of the IOMX Function 105 Table 7 1 MOTLoad Commands 121 Table 8 1 Default Processor Memory Map 125 Table 8 2 Suggested PPC Memory Map 127 Table 8 3 Default PCI Address Map 127 Table 8 4 Suggested PCI Memory Map 128 Table 8 5 Device Bank 1 I O Memo...

Page 11: ...ting for J99 41 Figure 2 11 MOTLoad System Startup 48 Figure 3 1 Component Layout 50 Figure 3 2 Front Panel Connector Cutouts Connectors and LED Indicators 51 Figure 4 1 CPCI 6115 Baseboard Block Diagram 68 Figure 5 1 CPCI 6115 MCPTM Block Diagram 90 Figure 5 2 Connector and Header Locations MXP Version 91 Figure 5 3 CompactFlash Jumper Settings J2 102 Figure 5 4 COM1 and COM2 Serial Port Jumpers ...

Page 12: ...CPCI 6115 CompactPCI Single Board Computer Installation and Use 6806800A68D List of Figures 10 ...

Page 13: ...s such as the CPCI 6115 MCPTM transition module Chapter 3 Controls LEDs and Connectors on page 49 describes face plate and on board connectors and their pin assignment On board headers and their settings are also discussed Chapter 4 Functional Description provides a description of the major components and functionality of the MCPN905 Chapter 5 Transition Module Preparation and Installation provide...

Page 14: ...hment BFL Board Fail CBGA Ceramic Ball Grid Array CHRP Computer Hardware Reference Platform CMC Common Mezzanine Card CPCI CompactPCI CPU Central Processing Unit CSR Control and Status Register DC Direct Current DDR Double Data Rate DMA Direct Memory Access DRAM Dynamic Random Access Memory DTE Data Terminal Equipment DTR Data Terminal Ready EIA Electronic Industries Alliance EIDE Enhanced Integra...

Page 15: ...dom Access Memory OS Operating System PC Payload Card PCB Printed Circuit Board PCI Peripheral Component Interconnect PCI X Peripheral Component Interconnect eXtended PF Port Format PICMG PCI Industrial Computer Manufacturer s Group PIM PMC I O Module PLD Programmable Logic Device PMC Peripheral Management Controller PMCIO PMC User I O PPC PowerPC PRP PowerPC Reference Platform PrPMC Processor PMC...

Page 16: ...Versa Module Eurocard VPD Vital Product Data Abbreviation Description Notation Description 0x00000000 Typical notation for hexadecimal numbers digits are 0 through F for example used for addresses and offsets 0b0000 Same for binary numbers digits are 0 and 1 bold Used to emphasize a word Screen Used for on screen output and code related elements or commands in body text Courier Bold Used to charac...

Page 17: ...s a hazardous situation which if not avoided may result in minor or moderate injury Indicates a property damage message No danger encountered Pay attention to important information Notation Description Date Description Replaces March 2008 Corrected description for Bank B flash memory to soldered not socketed 6806800A68C December 2007 Added Remote Start section Corrected default setting for J99 Add...

Page 18: ...uals and how we can make them better Mail comments to z Embedded Communications Computing Reader Comments DW164 2900 S Diablo Way Suite 190 Tempe Arizona 85282 z eccrc motorola com In all your correspondence please list your name position and company Be sure to include the title and part number of the manual and tell how you used it Then tell us your feelings about its strengths and weaknesses and...

Page 19: ... this manual is meant to complete the knowledge of a specialist and must not be used as replacement for qualified personnel Keep away from live circuits inside the equipment Operating personnel must not remove equipment covers Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal ...

Page 20: ... thus damage of the product When operating the product make sure that forced air cooling is available in the shelf Configuration Switches Jumpers Malfunction of the Product Switches marked as Reserved might carry production related functions and can cause the product to malfunction if their setting is changed Do not change settings of switches marked as reserved Damage of the Product Setting reset...

Page 21: ...ent integrity before installation Motorola Embedded Communications Computing ECC and our suppliers take significant steps to ensure there are no bent pins on the backplane or connector damage to the boards prior to leaving the factory Bent pins caused by improper installation or by inserting boards with damaged connectors could void the ECC warranty for the backplane or boards Damage of the Produc...

Page 22: ...nment Always dispose of used boards system components and RTMs according to your country s legislation and manufacturer s instructions Battery Board System Damage Danger of explosion if battery is replaced incorrectly Replace battery only with the same or equivalent type recommended by the equipment manufacturer Dispose of used batteries according to the manufacturer s instructions Il y a danger d...

Page 23: ...f ausschließlich für Anwendungen in der Telekommunikationsindustrie und im Zusammenhang mit Industriesteuerungen verwendet werden Einbau Wartung und Betrieb dürfen nur von durch Motorola ausgebildetem oder im Bereich Elektronik oder Elektrotechnik qualifiziertem Personal durchgeführt werden Die in diesem Handbuch enthaltenen Informationen dienen ausschließlich dazu das Wissen von Fachpersonal zu e...

Page 24: ...ng im Rahmen der erlaubten Grenzwerte bewegt Warnung Dies ist eine Einrichtung der Klasse A Diese Einrichtung kann im Wohnbereich Funkstörungen verursachen In diesem Fall kann vom Betreiber verlangt werden angemessene Maßnahmen durchzuführen Operation Beschädigung des Produktes Hohe Luftfeuchtigkeit und Kondensat auf der Oberfläche des Produktes können zu Kurzschlüssen führen Betreiben Sie das Pro...

Page 25: ...ostatische Entladung und unsachgemäßer Ein und Ausbau des Produktes kann Schaltkreise beschädigen oder ihre Lebensdauer verkürzen Bevor Sie das Produkt oder elektronische Komponenten berühren vergewissern Sie sich daß Sie in einem ESD geschützten Bereich arbeiten Beschädigung des Produktes Fehlerhafte Installation des Produktes kann zu einer Beschädigung des Produktes führen Verwenden Sie die Hand...

Page 26: ...s erlöschen lassen Kabel und Stecker Beschädigung des Produktes Bei den RJ 45 Steckern die sich an dem Produkt befinden handelt es sich entweder um Twisted Pair Ethernet TPE oder um E1 T1 J1 Stecker Beachten Sie dass ein versehentliches Anschließen einer E1 T1 J1 Leitung an einen TPE Stecker das Produkt zerstören kann z Kennzeichnen Sie deshalb TPE Anschlüsse in der Nähe Ihres Arbeitsplatzes deutl...

Page 27: ... 1 5 GB of DDR266 133 MHz SDRAM onboard memory Memory Controllers Provided by Marvell MV64360 System Memory Controller PCI Host Bridges Provided by Marvell MV64360 System Memory Controller Interrupt Controller Provided by Marvell MV64360 System Memory Controller PCI Interfaces One local PCI PCI X bus supporting 32 64 bit 33 66 MHz PCI or 66 133 MHz PCI X to PMC2 One local PCI bus supporting 32 bit...

Page 28: ...I O plus rear I O PMC 1 32 bit 33 MHz PCI Both slots support non Monarch Processor PMC modules Front Panel One asynchronous debug port via RJ 45 connector Recessed ABORT RESET switch CPU Activity and Board Fail LEDs Switch and blue LED in handle to support hot swap Ethernet RJ 45 connector with Status LEDs Debug Support Serial port with RS 232 interface Processor JTAG interface RESET and ABORT sig...

Page 29: ...stances in electrical and electronic equipment RoHS Table 1 2 Board Standard Compliances continued Standard Description Table 1 3 Board Variant Order Numbers Description Part Numbers CPCI 6115 220 867 MHz MPC7457 512 MB DRAM three Ethernet ports CPCI 6115 240 1 GHz MPC7457 512 MB DRAM CPCI 6115 270 1 GHz MPC7457 2 GB DRAM three Ethernet ports Table 1 4 Related Product Order Numbers Related Product...

Page 30: ...CPCI 6115 CompactPCI Single Board Computer Installation and Use 6806800A68D Introduction Ordering Information 28 ...

Page 31: ...oard The CPCI 6115 can be used in both a CompactPCI or a PICMG 2 16 compatible chassis It can be used only in a peripheral nonsystem slot The board employs an Intel 21555 PCI to PCI bridge for accessing additional components on adjacent PCI buses A fully implemented CPCI 6115 consists of the baseboard PMC cards and an optional transition module for rear I O 2 2 Unpacking and Inspecting the Board R...

Page 32: ...ecifications for the environmental and mechanical characteristics of the CPCI 6115 A complete functional description of the CPCI 6115 baseboard appears in Chapter 4 Functional Description Specifications for the optional PCI mezzanines can be found in the documentation for those modules You must make sure that the board when operated in your particular system configuration meets the environmental r...

Page 33: ...00 Hz 25 octaves min all 3 axis nonoperating Physical dimensions Baseboard only Height Depth Baseboard with front panel and connectors Height Depth Front panel width 6U Eurocard 9 2 in 233 mm 6 3 in 160 mm 10 3 in 262 mm 7 4 in 188 mm 0 8 in 20 mm Product Damage High humidity and condensation on the board surface causes short circuits Do not operate the board outside the specified environmental li...

Page 34: ... evaluate the thermal performance of a circuit board assembly it is necessary to test the board under actual operating conditions These operating conditions vary depending on system design While Motorola performs thermal analysis in a representative system to verify operation within specified ranges see Table 2 3 on page 33 you should evaluate the thermal performance of the board in your applicati...

Page 35: ...ference designators as shown in Figure 2 1 on page 34 Versions of the board that are not fully populated may not contain some of these components The preferred measurement location for a component may be junction case or air as specified in the table Junction temperature refers to the temperature measured by an on chip thermal device Case temperature refers to the temperature at the top center sur...

Page 36: ...Installation and Use 6806800A68D Hardware Preparation and Installation Thermal Requirements 34 Figure 2 1 CPCI 6115 Thermally Significant Components Primary Side J5 J3 J2 J1 U14 U13 U32 U159 U160 U10 U9 U8 U7 U6 U5 U4 U3 U2 U40 U22 U23 U146 U36 ...

Page 37: ...lled 2 4 1 Overview of Start up Procedure The following table lists the things you will need to do before you can use this board and tells where to find the information you need to perform each step Be sure to read this entire chapter including all Caution and Warning notes before you begin Figure 2 2 CPCI 6115 Thermally Significant Components Secondary Side U89 U96 U102 U101 Table 2 4 Startup Ove...

Page 38: ... configuration and ensure proper operation of the CPCI 6115 you may need to carry out certain hardware modifications before installing the module Most options on the CPCI 6115 are software configurable Configuration changes are made by setting bits in control registers after the board is installed in a system The control registers are described in the CPCI 6115 CompactPCI Single Board Computer Pro...

Page 39: ...er Jumper pins 1 2 for Stand Alone operation no CPCI bus J10 Flash Boot Bank Select Header No jumper or jumper pins 1 2 for Bank A 32 MB Jumper pins 2 3 for Bank B 8 MB J15 12 V Present Header Jumper pins 1 2 allows board operation without 12 V power J20 Safe Start ENV Header No jumper or jumper pins 1 2 for normal ENV settings Jumper pins 2 3 for safe ENV settings J25 SROM Initialization Enable H...

Page 40: ...ction A three pin header is located on the board to select the correct bus mode operation 60x or MPX No jumper or a jumper between pins 2 and 3 allows the board to be in MPX mode A jumper placed between pins 1 and 2 enables 60x mode Figure 2 3 Switch and Jumper Locations J17 J16 J98 J99 J6 SW1 U32 U36 J15 J10 J9 U22 SW2 J20 J25 Figure 2 4 Jumper Setting for J6 ...

Page 41: ...in a chassis with a system slot controller board This will result in unpredictable system operation 2 5 5 J10 Flash Bank Selection The flash memory is organized in two banks A and B Both banks are 32 bits wide and form a 32 bit flash bank Bank B offers a minimum of 8MB of soldered flash memory Bank A offers 32MB of soldered flash memory To enable Flash Bank A place a jumper across header pins 1 an...

Page 42: ...allows board operation without 12 V supplies No jumper implies that 12 V and 12 V are present at the backplane 2 5 7 J20 Safe Start Header A 3 pin header is used to select programmed or safe start settings No jumper or a jumper placed between pins 1 and 2 allows programmed settings e g VPD SPD to be used during boot A jumper placed between pins 2 and 3 allows the safe start settings Safe VPD SPD p...

Page 43: ...evice initialization via the I2 C SROM No jumper or a jumper placed between pins 2 and 3 disables the initialization sequence 2 5 9 J99 Flash Bank A Programming Enable Header To protect the contents of Flash Bank A a 2 pin header is used to enable or disable the programming of Flash Bank A A jumper across pins 1 and 2 enables writes to array blocks programming data or configuring lock bits No jump...

Page 44: ...rovides the clock and arbitration signals to the CPCI 6115 The chassis must provide 5 V 3 3 V and VIO to the CPCI 6115 and the BD_SEL pin P1 D15 in the chassis must be grounded 2 7 Installing Hardware The following sections discuss the placement of PMC mezzanine cards on the CPCI 6115 baseboard and the installation of the complete CPCI 6115 assembly into a CompactPCI chassis Before installing the ...

Page 45: ...for the installation procedure The procedure assumes the CPCI 6115 has already been installed in the chassis 2 7 1 Installing PMC Modules on the CPCI 6115 One dual wide one single wide or two single wide PCI mezzanine PMC modules can be mounted on the CPCI 6115 baseboard Each PMC slot has four connectors that provide a PCI interface to two PMC slots that provide a user I O to the backplane Refer t...

Page 46: ...or access to the board 3 Carefully remove the CPCI 6115 from the card slot and lay it flat with connectors J1 through J5 facing you 4 Remove the PMC filler plate from the front panel of the CPCI 6115 5 Set the PMC 2 voltage key to the desired position The PMC 1 I O voltage key is factory installed at the 5 V position since the IDE controller regulates 5 V I O Do not move the PMC 1 voltage key Pers...

Page 47: ...e on top of the baseboard The four connectors on the underside of the PMC module should then connect smoothly with the corresponding connectors J11 12 13 14 or J21 22 23 24 on the CPCI 6115 7 Insert the four short Phillips screws provided with the PMC through the holes on the bottom side of the CPCI 6115 into the PMC front bezel and rear standoffs Tighten the screws 8 Reinstall the CPCI 6115 assem...

Page 48: ...CI system signaling requirements and ensure the backplane does not bus J3 or J5 signals 5 Slide the CPCI 6115 into the appropriate slot Grasping the top and bottom injector handles be sure the module is well seated in the P1 through P5 connectors on the backplane Do not damage or bend connector pins 6 Secure the CPCI 6115 in the chassis with the screws provided making good contact with the transve...

Page 49: ... Whatever the baud rate some type of hardware handshaking either XON OFF or via the RTS CTS line is desirable if the system supports it 2 9 Applying Power After you have verified that all necessary hardware preparation has been done that all connections have been made correctly and that the installation is complete you can power up the system The MPU hardware and firmware initialization process is...

Page 50: ...ad Firmware Package User s Manual referenced in Appendix A Related Documentation The CPCI 6115 front panel has one ABORT RESET switch and three LED light emitting diode status indicators BFL CPU and HOT SWAP STATUS For more information on front panel operation refer to Chapter 4 Functional Description The CPCI 6115 also has status LEDs for SPEED LINK and ACTIVITY for Ethernet 2 on the front panel ...

Page 51: ...t of the on board jumper headers and connectors as well as the front panel connectors and LED indicators on the CPCI 6115 Also included are the pin assignments for the connectors and headers on the CPCI 6115 CompactPCI Single Board Computer Pinout listings can be found in Front Panel Connectors and LEDs on page 50 and On Board Connectors and Headers on page 52 ...

Page 52: ... board provides these status LEDs visible on the front panel of the CPCI 6115 Figure 3 1 Component Layout J98 J5 J3 J2 J1 J11 J13 J21 J23 J12 J14 J22 J24 U1 U14 U13 J95 J19 U32 U36 U159 U160 U10 U9 U8 U7 U6 U5 U4 U3 U2 U22 J17 J16 J99 J6 J15 J10 J9 SW2 J20 J25 SW1 Table 3 1 Front Panel LEDs LED Indicator Color Status CPU Green Glows solid TS signal of the processor bus is active hardware control B...

Page 53: ...reen Yellow Shows link status of the Ethernet link Ethernet 2 Glows solid green a valid 1000 megabit link Glows solid yellow a valid 10 100 megabit link Off No link ALT Green Glows solid activity is present on the Ethernet link Figure 3 2 Front Panel Connector Cutouts Connectors and LED Indicators Connector Header Pin Assignment CPCI 6115 Front Panel Asynchronous Serial Port J19 Table 3 2 on page ...

Page 54: ... are as follows Connector Header Location CPCI 6115 CompactPCI Connectors J1 J2 Table 3 4 on page 54 CPCI 6115 CompactPCI User I O Connector J3 Table 3 5 on page 54 CPCI 6115 CompactPCI Connector J4 N A CPCI 6115 CompactPCI User I O Connector J5 Table 3 7 on page 57 CPCI 6115 PCI Mezzanine Card PMC Connectors J11 J21 Table 3 8 on page 59 CPCI 6115 PCI Mezzanine Card PMC Connectors J12 J22 Table 3 ...

Page 55: ...mm hard metric type A connector with either 3 3 V or 5 V signaling J2 is a 110 pin AMP Z pack 2mm hard metric type B connector Each of these connectors conform to the CompactPCI specification The pinout for connectors J1 and J2 are implemented as defined in the CompactPCI specification for a 64 bit peripheral slot board Note that no reserved or bussed reserved pins are used by CPCI 6115 2 RTS OUTP...

Page 56: ...1 AD 6 AD 5 21 3 3 V AD 9 AD 8 M66EN C BE 0 20 AD 12 GND V IO AD 11 AD 10 19 3 3 V AD 15 AD 14 GND1 AD 13 18 SERR GND 3 3 V PAR C BE 1 17 3 3 V IPMB0_SCL IPMB0_SDA GND1 PERR 16 DEVSEL PCIXCAP V IO STOP LOCK 15 3 3 V FRAME IRDY BD_SEL TRDY KEY AREA Pins 12 14 11 AD 18 AD 17 AD 16 GND1 C BE 2 10 AD 21 GND 3 3 V AD 20 AD 19 9 C BE 3 IDSEL AD 23 GND1 AD 22 8 AD 26 GND V IO AD 25 AD 24 7 AD 30 AD 29 AD...

Page 57: ...SVP2A15 GND RSV RSV RSV 14 AD 35 AD 34 AD 33 GND AD 32 13 AD 38 GND V IO AD 37 AD 36 12 AD 42 AD 41 AD 40 GND AD 39 11 AD 45 GND V IO AD 44 AD 43 10 AD 49 AD 48 AD 47 GND AD 46 9 AD 52 GND V IO AD 51 AD 50 8 AD 56 AD 55 AD 54 GND AD 53 7 AD 59 GND V IO AD 58 AD 57 6 AD 63 AD 62 AD 61 GND AD 60 5 C BE 5 64EN V IO C BE 4 PAR64 4 V IO BRSVP2B4 C BE 7 GND C BE 6 3 RSV GND RSV RSV RSV 2 RSV RSV SYSEN a...

Page 58: ...CIO17 PMCIO16 10 9 PMCIO25 PMCIO24 PMCIO23 PMCIO22 PMCIO21 9 8 PMCIO30 PMCIO29 PMCIO28 PMCIO27 PMCIO26 8 7 PMCIO35 PMCIO34 PMCIO33 PMCIO32 PMCIO31 7 6 PMCIO40 PMCIO39 PMCIO38 PMCIO37 PMCIO36 6 5 PMCIO45 PMCIO44 PMCIO43 PMCIO42 PMCIO41 5 4 PMCIO50 PMCIO49 PMCIO48 PMCIO47 PMCIO46 4 3 PMCIO55 PMCIO54 PMCIO53 PMCIO52 PMCIO51 3 2 PMCIO60 PMCIO59 PMCIO58 PMCIO57 PMCIO56 2 1 IPMI_PWR PMCIO64 PMCIO63 PMCI...

Page 59: ...S1FX CS0 CS3FX CS1 DA2 MXDI MXDO 20 19 DMACK DIORDY DA1 MXCLK MXSYNC 19 18 DIOW DA0 TMCOM1 I2C_CLK I2C_DATA 18 17 GND DD14 DD15 DIOR DMARQ 17 16 DD9 DD10 DD11 DD12 DD13 16 15 DD5 DD6 GND DD7 DD8 15 14 DD0 DD1 DD2 DD3 DD4 14 13 PMCIO5 PMCIO4 PMCIO3 PMCIO2 PMCIO1 13 12 PMCIO10 PMCIO9 PMCIO8 PMCIO7 PMCIO6 12 11 PMCIO15 PMCIO14 PMCIO13 PMCIO12 PMCIO11 11 10 PMCIO20 PMCIO19 PMCIO18 PMCIO17 PMCIO16 10 9...

Page 60: ...r block select DA 2 0 drive register and data port address lines INTRQ drive interrupt request Signal Description COMxRD receive data COMxTD transmit data MXCLK clock for multiplexed data containing sync port control signals MXDI multiplexed data input MXDO multiplexed data output MXSYNC multiplexed data sync TMCOM1 enable COM1 Front panel RS232 transceiver PMC User I O PMCIO 64 1 PMC I O Miscella...

Page 61: ...rface In this case these pins are not connected on J13 factory configuration Table 3 8 PMC Connector Pin Assignments J11 J21 Pin J11 J21 Pin 1 TCK 12 V 2 3 GND INTA 4 5 INTB INTC 6 7 PRESENT 5 V 8 9 INTD PCI_RSVD 10 11 GND 3 3 Vaux 12 13 CLK GND 14 15 GND GNT XREQ0 16 17 REQ XGNT0 5 V 18 19 VIO AD31 20 21 AD28 AD27 22 23 AD25 GND 24 25 GND C BE3 26 27 AD22 AD21 28 29 AD19 5 V 30 31 VIO AD17 32 33 ...

Page 62: ...D 8 9 PCI_RSVD PCI_RSVD 10 11 MOT_RSVD 3 3 V 12 13 RST MOT_RSVD 14 15 3 3 V MOT_RSVD 16 17 PME GND 18 19 AD30 AD29 20 21 GND AD26 22 23 AD24 3 3 V 24 25 IDSEL AD23 26 27 3 3 V AD20 28 29 AD18 GND 30 31 AD16 C BE2 32 33 GND IDSELB 34 35 TRDY 3 3 V 36 37 GND STOP 38 39 PERR GND 40 41 3 3 V SERR 42 43 C BE1 GND 44 45 AD14 AD13 46 47 M66EN AD10 48 49 AD08 3 3 V 50 51 AD07 REQB_L 52 53 3 3 V GNTB_L 54 ...

Page 63: ... Note 1 GND 8 9 VIO PAR64 Note 1 10 11 AD63 Note 1 AD62 Note 1 12 13 AD61 Note 1 GND 14 15 GND AD60 Note 1 16 17 AD59 Note 1 AD58 Note 1 18 19 AD57 Note 1 GND 20 21 VIO AD56 Note 1 22 23 AD55 Note 1 AD54 Note 1 24 25 AD53 Note 1 GND 26 27 GND AD52 Note 1 28 29 AD51 Note 1 AD50 Note 1 30 31 AD49 Note 1 GND 32 33 GND AD48 Note 1 34 35 AD47 Note 1 AD46 Note 1 36 37 AD45 Note 1 GND 38 39 VIO AD44 Note...

Page 64: ...PMCIO3 PMCIO4 4 5 PMCIO5 PMCIO6 6 7 PMCIO7 PMCIO8 8 9 PMCIO9 PMCIO10 10 11 PMCIO11 PMCIO12 12 13 PMCIO13 PMCIO14 14 15 PMCIO15 PMCIO16 16 17 PMCIO17 PMCIO18 18 19 PMCIO19 PMCIO20 20 21 PMCIO21 PMCIO22 22 23 PMCIO23 PMCIO24 24 25 PMCIO25 PMCIO26 26 27 PMCIO27 PMCIO28 28 29 PMCIO29 PMCIO30 30 31 PMCIO31 PMCIO32 32 33 PMCIO33 PMCIO34 34 35 PMCIO35 PMCIO36 36 37 PMCIO37 PMCIO38 38 39 PMCIO39 PMCIO40 4...

Page 65: ... 0 1 JTAG COP header for use with third party MPC745x JTAG COP controllers The pin assignments for this header are as follows With no JTAG cable attached to J16 the CPU JTAG signals are routed to J17 as shown 51 PMCIO51 PMCIO52 52 53 PMCIO53 PMCIO54 54 55 PMCIO55 PMCIO56 56 57 PMCIO57 PMCIO58 58 59 PMCIO59 PMCIO60 60 61 PMCIO61 PMCIO62 62 63 PMCIO63 PMCIO64 64 Table 3 11 PMC Connector Pin Assignme...

Page 66: ... 6115 to select the boot flash bank No jumper or a jumper installed between pins 1 and 2 will route the BOOTCS signal to Flash Bank A and device CS0 to Flash Bank B A jumper installed between pins 2 and 3 routes BOOTCS to Flash Bank B and CS0 to Flash Bank A The pin assignments for this header are as follows 9 CPUTMS 10 NC 11 SRESET_L 12 NC 13 CPURST_L 14 KEY no pin 15 CHKSTPO_L 16 GND Table 3 13 ...

Page 67: ... a jumper between pins 2 and 3 selects the MPX bus mode The pin assignments for this header are as follows 3 5 16 SROM Initialization Enable Header A 3 pin 2 mm header is located on the board to enable disable the MV64360 SROM initialization A jumper from pins 1 to 2 enables the MV64360 device initialization via I2C SROM while no jumper or a jumper between pins 2 and 3 will disable this initializa...

Page 68: ...ng data or configuring lock bits The pin assignments for this header are as follows 3 5 18 12 V Present Header A 2 pin 0 1 header is located on the board to inform the CPCI 6115 whether the 12 V power supplies are present on the backplane If so then these power supplies are monitored for inclusion in the HLTY status If no jumper is installed the CPCI 6115 will assume that the 12 V supplies are pre...

Page 69: ...view of the CPCI 6115 followed by a detailed description of several blocks of circuitry Figure 4 1 shows a block diagram of the overall board architecture Detailed descriptions of other CPCI 6115 blocks including programmable registers in the ASICs and peripheral chips can be found in the MCPN905 CompactPCI Single Board Computer Programmer s Reference Guide and the Marvell MV64360 Reference Guide ...

Page 70: ...MB Flash A 32MB Flash B 8MB NVRAM RTC M48T37V Processor MPC7457 VPD SPD DDR SDRAM 3 bankS MV64360 System Controller PCI646U2 IDE Controller Device Bus 60x or MPX Bus 133 MHz Battery Single wide PMC PMC1 21555 Non Transparent PCI to PCI Bridge cPCI J5 cPCI J3 I2C Init User cPCI J1 J2 SROM PHY PHY TL16550 UART PHY Single wide PMC PMC2 Hot Swap Power Compact PCI Enet Enet IDE COM2 COM1 PMC1 I O PMC2 ...

Page 71: ...This is done through jumper controlled initialization The jumper setting selects either a planar configuration resistor initialization or an I2 C interface SROM initialization The CPCI 6115 board interfaces to the CompactPCI bus via the J1 and J2 connectors as specified in the PICMG 2 0 specification It draws 3 3 V and 5 V power and optionally 12 V power from the CompactPCI backplane through these...

Page 72: ... which may be allocated as L3 cache private memory or a combination of both The L3 cache bus is 72 bits wide 64 bits of data and 8 bits of parity The MPC7457 has an on chip 8 way set associative tag memory The external SRAMs are accessed through a dedicated L3 cache port which supports one bank of SRAM The L3 cache normally operates in copyback mode and supports system cache coherency through snoo...

Page 73: ...I O z One for the MV64360 integrated SRAM z One for the MV64360 internal registers SRAM Each window is defined by Base and Size registers and can decode up to 4 GB space except for the integrated SRAM which is fixed at 256 KB Refer to the MV64360 Data Sheet for additional information and programming details 4 3 4 2 MV64360 DDR SDRAM Interface The CPCI 6115 supports three banks of DDR SDRAM using 2...

Page 74: ...e IDE controller is populated The MV64360 PCI interfaces are fully PCI Rev 2 2 and PCI X compliant The MV64360 contains all the required PCI configuration registers All internal registers including the PCI configuration registers are accessible from the CPU bus or the PCI bus 4 3 4 5 MV64360 Integrated Gigabit Ethernet MACs The CPCI 6115 supports two 10 100 1000Base T full duplex Ethernet ports co...

Page 75: ... connected to one of the MV64360 interrupt input pins so that an interrupt is generated when the NMI_VAL count is reached The WDE pin is asserted after the watchdog timer is enabled and the 32 bit watchdog count expires The MV64360 holds WDE asserted for the duration of 16 system cycles after reset assertion The WDE pin is connected to the board reset logic so that a board reset will be generated ...

Page 76: ...interrupt requests The interrupts are routed to the MV64360 MPP pins from onboard resources as shown in Figure 4 2 on page 75 The external interrupt sources include the following z Onboard PCI device interrupts z PMC slot interrupts z RTC interrupt z Watchdog timer interrupts z ABORT switch interrupt z External UART interrupts z CompactPCI interrupts z Ethernet PHY interrupts For added information...

Page 77: ...pin on the CPCI 6115 board Table 4 2 MV64360 MPP Pin Function Assignments MPP Pin Number Input Output Function 0 I COM1 COM2 interrupts ORed 1 I Unused optionally 21555 interrupt can be routed here 2 I Abort interrupt 3 I RTC and Temperature Sensor interrupts ORed 4 I Unused 5 I Unused 6 I MV64360 WDNMI interrupt 7 I BCM5421S PHY interrupts ORed MPP 7 0 Interrupts 8 O PCI Bus 1 0 21555 Bridge gran...

Page 78: ...rd jumper Each option is described in the following table Using the SROM initialization method any of the MV64360 internal registers or other system components that is devices on the PCI bus can be initialized Initialization takes place by sequentially reading 8 byte address data pairs from the SROM and writing the 32 bit data to the decoded 32 bit address until the data pattern matching the last ...

Page 79: ...10 1010010 A4 11 1010011 A6 AD 4 Fixed 1 Internal 60x Bus Arbiter 0 Internal arbiter disabled 1 Internal arbiter enabled AD 5 Resistor 1 Internal Space Default Address 0 0x1400 0000 1 0xf100 0000 AD 7 6 Jumpers 01 CPU Bus Configuration 00 60x bus mode 01 MPX bus mode 10 Reserved 11 Reserved AD 8 Resistor 1 CPU Pads Calibration 0 Calibration Disabled 1 Calibration Enabled AD 9 Fixed 0 Multiple MV64...

Page 80: ...22 Resistors 000 DRAM read path control 000 100 DRAM running in sync mode 001 111 DRAM running in async mode AD 25 Fixed 0 Gigabit port2 Enable 0 Disable 1 Enable AD 28 26 Resistors 000 PCI_1 DLL control 000 DLL disable 001 Conventional PCI mode at 66MHz 101 PCI X mode at 133 MHz 110 PCI X mode at 66 MHz AD 31 29 PLD 101 PCI_0 DLL control 000 DLL disable 001 Conventional PCI mode at 66MHz 101 PCI ...

Page 81: ...3 MHz CLK WE 3 0 DP 3 0 X X DRAM PLL N Divider 7 4 3 0 X Not used in sync mode BADR 0 Resistor 1 DRAM PLL NP X Not used in sync mode BADR 1 Resistor 1 DRAM PLL HIKVCO X Not used in sync mode BADR 2 Resistor 1 DRAM PLL NP 0 PLL power down 1 PLL power up normal operation TxD0 6 1 X X DRAM PLL M Divider X Not used in sync mode TxD0 7 Resistor 0 JTAG Pad Calib Bypass 0 Normal Operation 1 Bypass pad ca...

Page 82: ...re using the System Register 2 FLASH_WP bit in the MV64360 when the jumper is installed There is a boot bank select jumper on the CPCI 6115 that selects either Flash Bank A or Bank B as the boot bank This jumper effectively routes the MV64360 BOOTCS pin to either Bank A Bank B and chip select CS0 to the other bank Bank B Bank A 4 3 7 NVRAM Real Time Clock Watchdog Timer An SGS Thompson M48T37V dev...

Page 83: ...ial EEPROM Devices The CPCI 6115 board contains three 8 KB serial EEPROM devices onboard one provides Vital Product Data VPD storage of the module hardware configuration one provides storage for user configuration data and the third optional provides initialization information for the MV64360 device The CPCI 6115 also has up to two 256 byte serial EEPROM devices onboard These 256 byte devices prov...

Page 84: ...ary or secondary z CompactPCI hot swap compliant z Secondary bus arbiter not used on CPCI 6115 z 3 3 V I O 5 V tolerant The 21555 provides a MicroWire serial ROM interface On power up or reset the 21555 can load its configuration registers from a serial EEPROM on this interface A 512 byte 93LC66A device is present on the CPCI 6115 for this purpose 4 3 15 CompactPCI Bus The CompactPCI bus interface...

Page 85: ... 75mm x 150mm with front panel z PMC Connectors J21 J22 J23 and J24 z Signaling Voltage Vio 3 3 V 5 V tolerant or 5 V selected by keying pin z Supported modes 32 64 bit 33 66 MHz PCI or 66 133 MHz PCI X z I O front panel and CompactPCI J5 rear panel In addition the PMC connectors are located such that a double width PMC may be installed in place of two single PMCs In this case the CPCI 6115 suppor...

Page 86: ...her describe CPCI 6115 interrupt related topics MONARCH The CPCI 6115 leaves the MONARCH pin floating causing any installed processor PMC to operate as a slave module Processor PMC monarch mode is not supported IDSELB These IDSELB pins are resistively coupled to the appropriate PCI AD pins REQB These REQB pins are routed to the appropriate PCI bus arbiters GNTB These GNTB pins are routed to the ap...

Page 87: ... PCI Bus 1 0 Table 4 7 MV64360 Interrupt Assignments GPP Group MV64360 Edge L evel Polarity Interrupt Source Notes 0 GPP 0 Level High COM1 COM2 3 GPP 1 Level Low Unused GPP 2 Level Low ABORT GPP 3 Level Low RTC Thermostat output 6 GPP 4 Level Low Unused GPP 5 Level Low Unused GPP 6 Level Low MV64360 WDNMI interrupt GPP 7 Level Low BCM5421S PHY 1 INTR BCM5421S PHY 2 INTR BCM5421S PHY 3 INTR 2 GPP 1...

Page 88: ...ned as a reset of the PowerPC The CPCI 6115 has these listed sources of reset z Power On undervoltage reset z Front panel reset switch z CompactPCI RESET signal z MV64360 Watchdog Timer z M48T37V Watchdog Timer z System Control Register bit The Processor RiscWatch HRESET signal can cause a CPU only reset 4 4 2 3 Machine Check The processor MCP signal is pulled high inactive 4 4 2 4 Soft Reset The ...

Page 89: ...he CompactPCI Hot Swap Specification PICMG 2 1 R2 0 Hot swap support is only applicable when the CPCI 6115 is installed into a CompactPCI peripheral slot 4 4 5 Hot Swap Process The CPCI 6115 may be safely inserted and extracted from a hot swap system chassis while power is applied Hot swap circuitry protects the board from electrical damage The BD_SEL signal from CPCI bus J1 pin D15 must be driven...

Page 90: ...moval Status bit REM_STAT in the CompactPCI Hot Swap Control Register to indicate an impending hot swap event z The 21555 contains an Insertion Status bit INS_STAT in the CompactPCI Hot Swap Control Register to indicate that the serial preload is complete and the Primary Lockout bit has been cleared indicating that the card is ready for host initialization ...

Page 91: ...and one RJ 45 connector for asynchronous serial port COM1 CompactPCI version or four RJ 45 connectors for asynchronous serial ports COM1 COM2 COM3 and COM4 MXP version Only COM1 and COM2 however are available on the CPCI 6115 SBC for use with the transition module An additional two serial ports and the one EIDE channel are available on J3 and J5 from the baseboard The transition module supports tw...

Page 92: ...2 Block Diagram The block diagram for the CPCI 6115 MCPTM is shown in the following figure Figure 5 1 CPCI 6115 MCPTM Block Diagram COM1 Compact Flash 1 RS232 Transceiver SROM Data User I O J5 Connector User I O J3 Connector IOMX Function Data Primary IDE Control 16 8 Mux 10 100 1000TX 10 100 1000TX PMC2 I O Module PMC1 I O Module REAR PANEL ...

Page 93: ...s used in conjunction with the CPCI 6115 baseboard It includes the following features IP version z One 50 pin Type II connector for IDE CompactFlash cards or microdrives z Two PMC I O modules PIM z Four asynchronous serial ports COM1 COM2 COM3 and COM4 z I O signal multiplexing IOMUX Figure 5 2 Connector and Header Locations MXP Version J8 J20 J5 J4 J3 J24 J10 J14 J11 J1 COM2 COM1 COM3 COM4 J6 J2 ...

Page 94: ... 45 connectors for COM1 COM2 COM3 and COM4 connections MXP version Note COM3 and COM4 are not used Table 5 2 On Board Connectors and Headers Connector Header Location CPCI 6115 MCPTM IDE CompactFlash Connector J1 Table 5 3 on page 93 CPCI 6115 MCPTM PMC I O Module 1 Host I O Connector J10 Table 5 4 on page 94 CPCI 6115 MCPTM PMC I O Module 2 Host I O Connector J20 Table 5 5 on page 95 CPCI 6115 MC...

Page 95: ... connectors on both the standard and MXP version of the CPCI 6115 MCPTM to provide an interface for two optional add on PMC I O modules Each module has an identical PMC I O connector and a unique Host I O connector All serial port signals are at TTL levels The pin assignments are as follows Table 5 3 CompactFlash IDE Connector Pin Assignments J1 Pin J1 Pin 1 GND NO CONNECT 26 2 DD3 DD11 27 3 DD4 D...

Page 96: ...d not use any pins on this connector Table 5 4 PMC I O Module 1 Host I O Connector Pin Assignments J10 Pin J10 Pin 1 IN1_DCD 12 V 2 3 IN1_RXD IN1_TXD 4 5 5 V IN1_DTR 6 7 IN1_DSR IN1_RTS 8 9 IN1_CTS 3 3 V 10 11 IN1_RI IN2_DCD 12 13 GND IN2_RXD 14 15 IN2_TXD IN2_DTR 16 17 IN2_DSR GND 18 19 IN2_RTS IN2_CTS 20 21 5 V IN2_RI 22 23 Not Connected Not Connected 24 25 Not Connected 3 3 V 26 27 Not Connecte...

Page 97: ...ble 5 5 PMC I O Module 2 Host I O Connector Pin Assignments J20 Pin J20 Pin 1 Not Connected 12 V 2 3 DD3 DD11 4 5 5 V DD4 6 7 DD12 DD5 8 9 DD13 3 3 V 10 11 DD6 DD14 12 13 GND DD7 14 15 DD15 CS1FX1_L 16 17 CS3FX1_L GND 18 19 DIOR_L DIOW_L 20 21 5 V DINTRQ1 22 23 MASTER SLAVE DRESET_L 24 25 IORDY 3 3 V 26 27 DA2 DA1 28 29 GND DA0 30 31 DASP DD0 32 33 PDIAG GND 34 35 DD1 DD8 36 37 5 V DD2 38 39 DD9 D...

Page 98: ...odule 2 Host I O Connector Pin Assignments J20 continued Pin J20 Pin Table 5 6 PMC I O Modules 1 and 2 PMC I O Connector Pin Assignments J14 24 Pin J14 J24 Pin 1 PMC IO1 PMC IO2 2 3 PMC IO3 PMC IO4 4 5 PMC IO5 PMC IO6 6 7 PMC IO7 PMC IO8 8 9 PMC IO9 PMC IO10 10 11 PMC IO11 PMC IO12 12 13 PMC IO13 PMC IO14 14 15 PMC IO15 PMC IO16 16 17 PMC IO17 PMC IO18 18 19 PMC IO19 PMC IO20 20 21 PMC IO21 PMC IO...

Page 99: ...O56 56 57 PMC IO57 PMC IO58 58 59 PMC IO59 PMC IO60 60 61 PMC IO61 PMC IO62 62 63 PMC IO63 PMC IO64 64 Table 5 6 PMC I O Modules 1 and 2 PMC I O Connector Pin Assignments J14 24 continued Pin J14 J24 Pin Table 5 7 User I O Connector Pinout J3 Pin Row A Row B Row C Row D Row E Pin 19 GND 12 V 12 V GND GND 19 18 LPa_DA TX1 LPa_DA TX1 GND LPa_DC LPa_DC 18 17 LPa_DB RX1 LPa_DB RX1 GND LPa_DD LPa_DD 17...

Page 100: ...C1IO60 PMC1IO59 PMC1IO58 PMC1IO57 PMC1IO56 2 1 IPMI_PWR PMC1IO64 PMC1IO63 PMC1IO62 PMC1IO61 1 Signal Description PMCIO PMC1IO 64 1 PMC1 I O signals 1 through 64 Ethernet PORTn_TXP high side of differential transmit data PORTn_TXN low side of differential transmit data PORTn_RXP high side of differential receive data PORTn_RXN low side of differential receive data Table 5 7 User I O Connector Pinou...

Page 101: ...MC2IO62 PMC2IO61 1 Signal Descriptions PMCIO PMC2IO 1 64 PMC 2 I O signals 1 through 64 EIDE Primary Port ATA 2 DIORA_L I O read DIOWA_L I O write DIORDYA indicates drive ready for I O DD 15 0 IDE data lines CS1FXA_L chip select drive 0 or command register block select CS3FXA_L chip select drive 1 or command register block select DA 2 0 drive register and data port address lines DRESET_L drive res...

Page 102: ... COM1DIR jumper is a two position three pin jumper which controls the origin of the serial port In one position COM1 from the CPCI 6115 is enabled and thereby disabling it on the CPCI 6115 front panel connector In the other position the connector is redirected to the PMC I O module 1 The COM2DIR jumper is a two position three pin jumper which controls the origin of the serial port In one position ...

Page 103: ...e other end is available through Motorola This can be ordered through Motorola by requesting the following part number MRJ45DB9ADP 01 works with either a Motorola or Intel CPU Connecting an CPCI 6115 to a PC terminal requires that the adapter described above be attached to a standard RJ 45 to RJ 45 shielded cable with straight through signaling The pinout information for this adapter is in the fol...

Page 104: ...e PIM device becomes the Slave By setting a jumper across pins 2 and 3 on jumper J2 the PIM device becomes the Master and the CompactFlash device becomes the Slave If no jumper is installed the board will default to the CompactFlash as the Master device 5 6 2 COM1 and COM2 Asynchronous Serial Ports Jumpers The asynchronous serial ports COM1 and COM2 are configured permanently as data circuit termi...

Page 105: ...sition module There are certain differences between the IP version and the CompactPCI model that are explained in the subsections where those differences apply 5 7 1 IDE Flash The CPCI 6115 SBC supports a single IDE channel routed to the J5 User I O connector The CPCI 6115 MCPTM contains one 50 pin Type II connector which supports a removable IDE CompactFlash memory card on the primary IDE channel...

Page 106: ...ddress for this EEPROM is A8 but optional resistors can be used allowing population options to configure this part to respond to any standard I2C address 5 7 5 PMC I O Modules CPCI 6115 SBC supports two single wide PMC sites Each site provides four 64 pin EIA E700 AAAB connectors to interface to a 32 64 bit IEEE P1386 1 PMC One of the four connectors is dedicated to user I O Two PMC I O modules ar...

Page 107: ...here are four pins that are used for the IOMX function MXCLK MXSYNC MXDO and MXDI MXCLK is the 10 MHz bit clock for the time multiplexed data lines MXDO and MXDI MXSYNC is asserted for one bit time at Time Slot 15 by the CPCI 6115 SBC MXSYNC is used by the CPCI 6115 MCPTM to synchronize with the CPCI 6115 SBC MXDO is the time multiplexed output line from the CPCI 6115 and MXDI is the time multiple...

Page 108: ...ng MXCLK MXSYNC MXDO and MXDI are illustrated by the following figure 4 RTS4 4 RI3 5 DTR4 5 CTS4 6 Reserved 6 DSR4 7 Reserved 7 DCD4 8 Reserved 8 CTS2 9 DTR1 9 RI4 10 DTR2 10 RI1 11 Reserved 11 DSR1 12 Reserved 12 DCD1 13 Reserved 13 RI2 14 Reserved 14 DSR2 15 Reserved 15 DCD2 Figure 5 6 P2MX Signal Timings Serial Port Signal Descriptions CTSn clear to send DCDn data carrier detected DSRn data set...

Page 109: ... located on the CPCI 6115 SBC is connected to the PMC I O module through the standard 64 bits of PMC user I O The PMC I O module must then loop the serial port back out on its host I O connector This approach allows the serial debug port to be assigned to any of the 64 PMC user I O lines The mating PMC I O module maps those lines onto the CPCI 6115 MCPTM serial channels It is expected that future ...

Page 110: ...ups of I O passed from the CPCI 6115 SBC to the CPCI 6115 MCPTM through the CompactPCI J3 and J5 connectors MCxx905 SBC host I O PMC1 I O and PMC2 I O CPCI 6115 SBC host I O functions are designed into the CPCI 6115 SBC and their presence or absence is determined when that board is built This I O cannot be configured at Figure 5 7 CPCI 6115 MCPTM Serial Ports 1 and 2 COM1 rear panel COM2 rear pane...

Page 111: ...C PMC sites To accommodate the pluggable nature of a PMC a custom form factor pluggable I O module is presented here A physical representation of the CPCI 6115 MCPTM and I O modules is shown below 5 7 8 PMC I O Module Form Factor The PMC I O module form factor is identical to the single wide PMC form factor with the following differences z Shorter by 80mm z Deletes the 5 V and 3 3 V keys z Pn1 and...

Page 112: ...d board may be implemented in a host I O module This functionality is special to the host in this case the CPCI 6115 SBC and so the host I O module is not a universal module However if the host I O connector pinout is reused on future transition modules the host I O module may be reused If possible optional host I O routed to the host I O connector will be terminated in such a fashion that the hos...

Page 113: ...rocedure 2 Perform an operating system shutdown Turn the AC or DC power off and remove the AC cord or DC power lines from the system 3 Remove chassis or system cover s as necessary for access to the CompactPCI 4 Carefully remove the transition module from its CompactPCI card slot and lay it flat on a stable surface 5 Remove the PIM filler from the front panel of the transition module Product Damag...

Page 114: ... board alignment 7 Insert the four short Phillips screws provided with the PIM through the holes on the bottom side of the transition module into the PIM front bezel and rear standoffs Tighten the screws 8 With the CPCI 6115 MCPTM in the correct vertical position that matches the pin positioning of the backplane carefully slide the transition module into the appropriate slot and seat tightly into ...

Page 115: ...r access to the chassis backplane 3 With the CPCI 6115 MCPTM in the correct vertical position that matches the pin positioning of the backplane carefully slide the transition module into the appropriate slot and seat tightly into the backplane Refer to Figure 5 10 on page 114 for the correct board connector orientation 4 Secure in place with the screws provided making good contact with the transve...

Page 116: ...er is applied in a hot swap capable backplane the CPCI 6115 MCPTMs are not hot swap capable Inserting or removing the transition module while the CPU board is active may affect the normal operation of the CPU board Even in a hot swap capable chassis the CPU back end power should be switched off or the chassis power shut down prior to inserting or removing its corresponding transition module Figure...

Page 117: ...rned to the register When the host writes a new command to the register it must clear the ownership flag to indicate the register contains a command to be processed z A command opcode This field is a numeric field that specifies the command the host wants performed z An error flag which is used to provide command completion status to the host CPU z A command options field This field further qualif...

Page 118: ...3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 O W N Command opcode E R R Command Options Command Data Result Bit Number Description Bit 0 The ownership flag OWN A value of 1 indicates the host owns the register A value of 0 indicates that the local CPU owns the register Bits 1 to 7 7 bit command opcode field Each command is described in more detail in the MOTLoad ...

Page 119: ...o serve in some respects as a test suite providing individual tests for certain devices MOTLoad is controlled through an easy to use UNIX like command line interface The MOTLoad software package is similar to many end user applications designed for the embedded market such as the real time operating systems currently available Refer to the MOTLoad Firmware Package User s Manual listed in Appendix ...

Page 120: ...iven standard Test applications are validation tests Validation is conformance to a specification Most MOTLoad tests are designed to directly validate the functionality of a specific SBC subsystem or component These tests validate the operation of such SBC modules as dynamic memory external cache NVRAM real time clock etc All MOTLoad tests are designed to validate functionality with minimum user i...

Page 121: ...e default MOTLoad serial port settings are 9600 baud 8 bits no parity 7 7 1 Command Line Interface The MOTLoad command line interface is similar to a UNIX command line shell interface Commands are initiated by entering a valid MOTLoad command a text string at the MOTLoad command line prompt and pressing the carriage return key to signify the end of input MOTLoad then performs the specified action ...

Page 122: ...sts and utilities Example CPCI 6115 help For help with a specific test or utility the user can enter the following at the MOTLoad prompt help command_name The help command also supports a limited form of pattern matching Refer to the help command page Example CPCI 6115 help testRam Usage testRam aPh bPh iPd nPh tPd v Description RAM Test Directory Argument Option Description a Ph Address to Start ...

Page 123: ...orted by MOTLoad may or may not employ the full command set Typing help at the MOTLoad command prompt displays all commands supported by MOTLoad for a given product Table 7 1 MOTLoad Commands Command Description as One Line Instruction Assembler bcb bch bcw Block Compare Byte Halfword Word bdTempShow Display Current Board Temperature bfb bfh bfw Block Fill Byte Halfword Word blkCp Block Copy blkFm...

Page 124: ...ice Configuration Data gd Go Execute User Program Direct Ignore Break Points gevDelete Global Environment Variable Delete gevDump Global Environment Variable s Dump NVRAM Header Data gevEdit Global Environment Variable Edit gevInit Global Environment Variable Area Initialize NVRAM Header gevList Global Environment Variable Labels Names Listing gevShow Global Environment Variable Show gn Go Execute...

Page 125: ...onfiguration Header Register pciShow Display PCI Device Configuration Header Register pciSpace Display PCI Device Address Space Allocation ping Ping Network Host portSet Port Set portShow Display Port Device Configuration Data rd User Program Register Display reset Reset System rs User Program Register Set set Set Date and Time sromRead SROM Read sromWrite SROM Write sta Symbol Table Attach stl Sy...

Page 126: ...Loopback testStatus Display the Contents of the Test Status Table testSuite Execute Test Suite testSuiteMake Make Create Test Suite testThermoOp Thermometer Temperature Limit Operational Test testThermoQ Thermometer Temperature Limit Quick Test testThermoRange Test That Board Temperature Is Within Range testWatchdogTimer Tests the accuracy of the watchdog timer device tftpGet TFTP Get tftpPut TFTP...

Page 127: ... points of view Detailed memory maps can be found in the MCPN905 CompactPCI Single Board Computer Programmer s Reference Guide MCPN905A PG 8 2 1 Default Processor Memory Map The MV64360 presents a default CPU memory map following RESET negation The following table shows the default Memory Map from the point of view of the Processor Address bits 35 32 are only relevant for the MPC7457 extended addr...

Page 128: ...MB Device CS2 1E00 0000 1FFF FFFF 32 MB Unassigned 2000 0000 21FF FFFF 32 MB PCI Bus 1 I O 2200 0000 23FF FFFF 32 MB PCI Bus 1 Memory Space 0 2400 0000 25FF FFFF 32 MB PCI Bus 1 Memory Space 1 2600 0000 27FF FFFF 32 MB PCI Bus 1 Memory Space 2 2800 0000 29FF FFFF 32 MB PCI Bus 1 Memory Space 3 2A00 0000 41FF FFFF 384 MB Unassigned 4200 0000 4303 FFFF 256 KB MV64360 Integrated SRAM 4304 0000 F0FF F...

Page 129: ... CFFF FFFF 512 MB PCI Bus 1 Memory Space F000 0000 F07F FFFF 8 MB PCI Bus 0 I O Space F080 0000 F0FF FFFF 8 MB PCI Bus 1 I O Space F100 0000 F10F FFFF 1 MB MV64360 Internal Registers 1 F110 0000 F11F FFFF 1 MB Device CS1 I O System Regs NVRAM RTC UART F200 0000 F5FF FFFF 64 MB Flash Bank A FF800 0000 FFFF FFFF 8 MB Flash Bank B Table 8 3 Default PCI Address Map PCI Address Size Definition Notes St...

Page 130: ...0 Integrated SRAM 4304 0000 F1FF FFFF 2800 MB Unassigned F200 0000 F3FF FFFF 32 MB PCI Bus 1 P2P Memory Space 1 F400 0000 FEFF FFFF 176 MB Unassigned FF00 0000 FF7F FFFF 8 MB Device CS3 FF80 0000 FFFF FFFF 8 MB Boot Flash 1 Table 8 3 Default PCI Address Map continued PCI Address Size Definition Notes Start End Table 8 4 Suggested PCI Memory Map PCI Address Size Definition Start End 0000 0000 top_d...

Page 131: ...transparent PCI to PCI bridge to interface between the local PCI bus and the CompactPCI bus The 21555 is different from traditional PCI to PCI bridges in that it uses address translation instead of a flat address map between primary and secondary PCI buses In the CPCI 6115 configuration the primary bus is the CompactPCI bus and the secondary bus is the CPCI 6115 local bus Downstream transactions a...

Page 132: ...een these two address maps when forwarding transactions upstream or downstream Recommendations for CompactPCI mapping can be found in the MCPN905 CompactPCI Single Board Computer Programmer s Reference Guide MCPN905A PG 8 2 9 L1 L2 and L3 Cache The CPCI 6115 supports the MPC7457 processor on chip L1 and L2 caches with 2 MB of external L3 cache installed The CPCI 6115 L3 memory consists of two 8 me...

Page 133: ... for the listed document is provided Please note that while these sources have been verified the information is subject to change without notice Table A 1 Motorola ECC Documents Document Title Publication Number MCPN905 CompactPCI Single Board Computer Programmer s Reference Guide MCPN905A PG MOTLoad Firmware Package User s Manual MOTLODA UM Table A 2 Manufacturers Documents Document Title and Sou...

Page 134: ...6U2 pdf Table A 2 Manufacturers Documents continued Document Title and Source Publication Number or Search Term Table A 3 Related Specifications Document Title and Source Publication Number IEEE http standards ieee org catalog IEEE Standard for Local Area Networks Carrier Sense Multiple Access with Collision Detection CSMA CD Access Method and Physical Layer Specifications Institute of Electrical ...

Page 135: ... 2665 Telephone 1 800 745 7323 http www mkp com ISBN 1 55860 394 8 Compact PCI Specification PCI Industrial Manufacturers Group PICMG http www picmg com PICMG 2 0 R3 0 10 1 99 CompactPCI Hot Swap Specification PCI Industrial Manufacturers Group PICMG http www picmg com PICMG 2 1 R2 0 1 17 01 CompactPCI Packet Switching Backplane Specification PCI Industrial Manufacturers Group PICMG http www picmg...

Page 136: ...CPCI 6115 CompactPCI Single Board Computer Installation and Use 6806800A68D Related Documentation Related Specifications 134 ...

Page 137: ...t 115 firmware as initialization agent 47 H hardware configuration 36 hardware management components 115 help command MOTLoad 120 I inspecting shipment 29 J J10 jumper settings 39 J3 connector 905 pin assignments 55 J5 connector 905 pin assignments 57 jumper settings baseboard 37 L list of commands MOTLoad 121 M manufacturer s documents 131 memory maps 125 MOTLoad command characteristics 119 comma...

Page 138: ...nector 905 55 J3 connector TM 97 J5 connector 905 57 J5 connector TM 98 J6 header 905 65 J9 header 905 64 J99 header 905 66 power requirements 29 preparation baseboard 36 product how to order 27 R related specifications 132 Remote Start command options field 115 reset sources 86 S software OpenHPI 115 specification compliancy 26 specifications CPCI 6115 30 Stand Alone Operating Mode J10 39 standar...

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