Motorola CPCI-6020 Installation And Use Manual Download Page 83

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CPCI-6020 CompactPCI Single Board Computer Installation and Use (6806800A51C

)

Functional Description

Block Diagram

4.2

Block Diagram

The following figure is a block diagram of the CPCI-6020 architecture.

Figure 4-1

Block Diagram

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Summary of Contents for CPCI-6020

Page 1: ...l service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE INSPECTION Remotely inspect equipment before purchasing with our interactive website at www instraview com LOOKING FOR MORE INFORMATION Visit us on the web at www artisantg com for more information on ...

Page 2: ...CPCI 6020 CompactPCI Single Board Computer Installation and Use 6806800A51C February 2008 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 3: ...or personal use or referenced in another document as a URL to a Motorola website The text itself may not be published commercially in print or electronic form edited translated or otherwise altered without the permission of Motorola It is possible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not availab...

Page 4: ...hermal Requirements 39 2 6 Hardware Configuration 39 2 7 CPCI 6020 Baseboard Preparation 40 2 8 Jumper Settings 41 2 8 1 Flash Bank Selection 41 2 8 2 Harrier Power Up Configuration Header 42 2 8 3 PMC 66 MHz Disable 42 2 8 4 Enable Disable 12 V and 12 V Use 42 2 8 5 Enable Disable Lockdown of One or More Flash Blocks for Bank A 43 2 8 6 Enable Write Protect for Entire Flash on Bank A 43 2 8 7 Rem...

Page 5: ... 4 2 CompactPCI User I O Connector 63 3 4 3 CompactPCI User I O Connector 64 3 4 4 CompactPCI User I O Connector 65 3 4 5 Memory Mezzanine Connectors 67 3 4 6 PCI Mezzanine Card PMC Connectors 68 3 4 7 Lock Down Flash Enable Jumper 72 3 4 8 PMC 66 Mhz Disable Jumper 73 3 4 9 Remote Switch Connector 73 3 4 10 Flash Write Protect Enable Jumper 73 3 4 11 Harrier Power Up Configuration 74 3 4 12 Xport...

Page 6: ... Harrier A Channel 2 NVRAM RTC External Register Set 92 4 8 4 Harrier A Channel 3 92 4 8 5 Harrier B Channel 0 1 2 and 3 92 4 9 Other Harrier Resources 93 4 9 1 I2C Bus Resources Serial EEPROM 93 4 9 2 Asynchronous Serial Ports 93 4 9 3 32 Bit Timers 93 4 9 4 Watchdog Timers 93 4 10 Other Board Resources 94 4 10 1 Miscellaneous Control and Status 94 4 10 2 Clock Generator 94 4 10 3 Onboard Power S...

Page 7: ...s 108 5 4 PPCBug Implementation 108 5 5 MPU Hardware and Firmware Initialization 108 5 6 Using PPCBug 110 5 7 Debugger Commands 110 5 8 Diagnostic Tests 114 6 RAM500 Memory Expansion Module 117 6 1 Overview 117 6 2 RAM500 Description 117 6 3 RAM500 Module Installation 118 6 4 Features 119 6 4 1 SROM 119 6 4 2 Host Clock Logic 120 6 4 3 Serial Presence Detect SPD Data 120 6 5 RAM500 Connectors 120 ...

Page 8: ...e Connector 143 7 9 3 10BaseT 100BaseTx Connectors 146 7 9 4 COM1 Connector 146 7 9 5 COM2 Header 147 7 9 6 EIDE Header 147 7 9 7 Floppy Port Header 148 7 9 8 5VDC Power Connector 148 7 9 9 Keyboard Mouse Connector 149 7 9 10 Sync Async Serial Ports 149 7 9 11 Speaker Output Header 150 8 CNFG and ENV Commands 151 8 1 Overview 151 8 2 CNFG Configure Board Information 151 8 3 ENV Set Environment 152...

Page 9: ...CPCI 6020 CompactPCI Single Board Computer Installation and Use 6806800A51C Contents 8 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 10: ...le 3 15 J12 PMC Connector J12 Pin Assignments 69 Table 3 16 PMC Connector J13 Pin Assignments 70 Table 3 17 PMC Connector J14 Pin Assignments 71 Table 3 18 J17 Lock Down Flash Enable Jumper 72 Table 3 19 J21 PMC 66 MHz Disable Jumper 73 Table 3 20 J19 Remote Switch Connector 73 Table 3 21 J20 Flash Write Protect Enable Jumper 73 Table 3 22 J22 Harrier Power Up Configuration Header Pin Assignments ...

Page 11: ... O Module PMC I O Connector Pin Assignments 144 Table 7 6 10BaseT 100BaseTx Connector Pin Assignments 146 Table 7 7 COM1 Connector Pin Assignments 146 Table 7 8 COM2 Header Pin Assignments 147 Table 7 9 EIDE Header Pin Assignments 147 Table 7 10 Floppy Header Pin Assignments 148 Table 7 11 5Vdc Power Connector 148 Table 7 12 Keyboard Mouse Connector Pin Assignments 149 Table 7 13 Sync Async Serial...

Page 12: ...ure 4 2 Reset Block Diagram 96 Figure 4 3 Serial Port Signal Multiplexing 101 Figure 4 4 P2MX Signal Timings 103 Figure 4 5 PMC Interface Module Layout 104 Figure 7 1 Block Diagram 128 Figure 7 2 Component Layout 129 Figure 7 3 Rear Panel Connectors Cut outs 130 Figure 7 4 Ports 3 and 4 Header Settings 133 Figure 7 5 EIA 232 D DCE Ports 3 and 4 Configuration 135 Figure 7 6 EIA 232 D DTE Ports 3 an...

Page 13: ...CPCI 6020 CompactPCI Single Board Computer Installation and Use 6806800A51C List of Figures 12 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 14: ...LEDs and Connectors provides illustrations of the board components and face plate details This chapter also gives descriptions for the onboard and front panel LEDs and connections and pinout information for connectors headers and jumpers Chapter 4 Functional Description describes the major features of the CPCI 6020 baseboard and the CPCI 6020 MCPTM 01 transition module These descriptions include b...

Page 15: ...Hardware Reference Platform CMOS Complementary metal oxide semiconductor DCE Data Circuit Termination DTE Data Terminal Equipment EIDE Enhanced Integrated Design Electronics EMI Electro Magnetic Interference ESD Electro Static Discharge FDD Floppy Disk Drive GB Gigabyte HA High Availability HDD Hard Disk Drive HSC Hot Swap Controller IOMUX I O Signal Multiplexing ISA Industry Standard Architecture...

Page 16: ...tal Product Data Abbreviation Description Notation Description 0x00000000 Typical notation for hexadecimal numbers digits are 0 through F for example used for addresses and offsets 0b0000 Same for binary numbers digits are 0 and 1 bold Used to emphasize a word Screen Used for on screen output and code related elements or commands in body text Courier Bold Used to characterize user input and to sep...

Page 17: ...a hazardous situation which if not avoided may result in minor or moderate injury Indicates a property damage message No danger encountered Pay attention to important information Notation Description Part Number Publication Date Description 6806800A36A First release Replaces MCP820 SBC 6806800A36B January 2007 J24 Xport flash bank select header description corrected 6806800A36C January 2008 Remove...

Page 18: ...and how we can make them better Mail comments to z Motorola Inc Embedded Communications Computing 2900 South Diablo Way Suite 190 Tempe Arizona 85282 z reader comments ecc mot com In all your correspondence please list your name position and company Be sure to include the title part number and revision of the manual and tell how you used it Artisan Technology Group Quality Instrumentation Guarante...

Page 19: ...CPCI 6020 CompactPCI Single Board Computer Installation and Use 6806800A51C About this Manual 18 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 20: ...e of a specialist and must not be used as replacement for qualified personnel Keep away from live circuits inside the equipment Operating personnel must not remove equipment covers Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Do not install substitute parts or ...

Page 21: ...compliance with the above mentioned requirements A proper installation in a compliant system will maintain the required performance Use only shielded cables when connecting peripherals to assure that appropriate radio frequency emissions compliance is maintained Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 22: ...he operating system or other software running on the board has been properly shut down may cause corruption of data or file systems Make sure all software is completely shut down before removing power from the board or removing the board from the chassis Data Loss Although a command that allows erasing and reprogramming of flash memory is available note that reprogramming any portion of the CPCI 6...

Page 23: ...to module components by verifying the proper slot usage for your configuration Check the icons and colored card rails for slot purpose prior to installing a module Damage to the Product Backplane or System Components Bent pins or loose components can cause damage to the product the backplane or other system components Therefore carefully inspect the product and the backplane for both pin and compo...

Page 24: ...e susceptible to excessive interference Rear Transition Module Product Damage Inserting or removing modules in a non hot swap chassis with the power applied may result in damage to the module components The CPCI 6020 MCPTM 01 is not a hot swap board but it may be installed in a hot swap chassis with power applied if the corresponding CPCI 6020 is removed from the front slot first Environment Alway...

Page 25: ...CPCI 6020 CompactPCI Single Board Computer Installation and Use 6806800A51C Safety Notes 24 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 26: ...mmunikationsindustrie und im Zusammenhang mit Industriesteuerungen verwendet werden Einbau Wartung und Betrieb dürfen nur von durch Motorola ausgebildetem oder im Bereich Elektronik oder Elektrotechnik qualifiziertem Personal durchgeführt werden Die in diesem Handbuch enthaltenen Informationen dienen ausschließlich dazu das Wissen von Fachpersonal zu ergänzen können dieses jedoch nicht ersetzen Ha...

Page 27: ...r Anwender die Genehmigung zum Betrieb des Produktes verliert Boardprodukte werden in einem repräsentativen System getestet um zu zeigen dass das Board den oben aufgeführten EMV Richtlinien entspricht Eine ordnungsgemässe Installation in einem System welches die EMV Richtlinien erfüllt stellt sicher dass das Produkt gemäss den EMV Richtlinien betrieben wird Verwenden Sie nur abgeschirmte Kabel zum...

Page 28: ...plane auf entweder 3 3 V oder 5 V gemäss den jeweiligen Systemanforderungen Datenverlust Das Herunterfahren oder die Deinstallation eines Boards bevor das Betriebssystem oder andere auf dem Board laufende Software ordnungsmemäss beendet wurde kann zu partiellem Datenverlust sowie zu Schäden am Filesystem führen Stellen Sie sicher dass sämtliche Software auf dem Board ordnungsgemäss beendet wurde b...

Page 29: ...arbeiten Beschädigung des Boards Die Installation oder Deinstallation eines nicht HA fähigen Modules in ein System aus einem System dessen Spannungsversorgung eingeschaltet ist kann zur Beschädigung des Modules führen Stellen Sie sicher dass das Modul HA fähig ist Beschädigung des Produktes Vermeiden Sie eine mögliche Beschädigung des Modules indem Sie sicherstellen dass der zu verwendende Slot fü...

Page 30: ...inien hinsichtlich EMV erfüllt sind Sobald die EMV Abschirmung des Chassis durchlässig wird können Boards Module sowohl starke Störstrahlung aussenden als auch selber starker Störstrahlung ausgesetzt sein Rear Transition Module Beschädigung des Produktes Die Installation oder Deinstallation eines Modules in ein nicht Hot Swap fähiges System aus einem nicht Hot Swap fähigem System dessen Spannungsv...

Page 31: ...CPCI 6020 CompactPCI Single Board Computer Installation and Use 6806800A51C Sicherheitshinweise 30 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 32: ...nterrupt Controller Harriers MPIC Multi Processor Interrupt Controller PCI Interfaces Dual 33 MHz 32 64 bit PCI 2 1 busses bridging from the processor bus one PCI Bus also capable of 66 MHz 3 3 V 5 V universal signaling interface One PMC slot Connection through the J4 connector to the backplane Address data parity per PCI specification Ethernet Interface Two 10BaseT 100BaseTx interfaces based on I...

Page 33: ...ne PS 2 Mouse Floppy disk controller PMC Slot One 32 64 bit PMC slot with front panel I O plus rear I O 33 66 MHz capable Local PCI Bus Expansion Local 64 bit PCI bus routed to J4 to support additional PCI to PCI bridge and CompactPCI bus on companion card Front Panel Asynchronous COM port via RJ 45 10 100 MB Ethernet via RJ 45 Two USB ports Recessed RESET and ABORT switches CPU Activity and Board...

Page 34: ...6 NEBS Standard GR 1089 CORE EMC requirements legal on system level predefined Motorola system NEBS Standard GR 63 CORE ETSI EN 300 019 series Environmental Requirements Directive 2002 95 EC Directive on the restriction of the use of certain hazardous substances in electrical and electronic equipment RoHS Table 1 2 Board Standard Compliances continued Standard Description Model Number Description ...

Page 35: ...ory 512 MB RAM5006E 020 Bottom memory 512 MB RAM500 005 Top memory 128 MB 5E RAM500 015 Bottom memory 128 MB 5E RAM500 006 Top memory 256 MB 5E RAM500 016 Bottom memory 256 MB 5E RAM500 010 Top memory 512 MB 5E RAM500 020 Bottom memory 512 MB 5E CFLASH5E 256 CompactFlash 256 MB CFLASH5E 512 CompactFlash 512 MB CPCI 60206E MCPTM 01 CPCI 6020 Rear Transition Module CPCI 6020 MCPTM 01 CPCI 6020 Rear ...

Page 36: ...ne card PMC for added versatility z One or two RAM500 SDRAM memory mezzanines per mezzanine site two sites available for a maximum of 2 GB of added memory z One CPCI 6020 MCPTM 01 rear transition module for support of the mapped I O from the CPCI 6020 baseboard to the J3 and J5 CompactPCI connectors 2 2 Unpacking and Inspecting the Board Read all notices and cautions prior to unpacking the product...

Page 37: ...ems are missing contact customer service immediately Table 2 1 Startup Overview Task Page Unpack the hardware Chapter 2 Unpacking and Inspecting the Board on page 35 Configure the hardware by setting jumpers on the boards Chapter 2 Jumper Settings on page 41 Ensure CompactFlash card is installed if required Chapter 2 CompactFlash Memory Card Installation on page 46 Ensure memory mezzanines are pro...

Page 38: ...m solution center for connecting port 1 through custom build options two USB ports two UART ports one may be run to front and two synchronous COM ports 2 5 Environmental and Power Requirements You must make sure that the blade when operated in your particular system configuration meets the environmental requirements specified in the next section 2 5 1 Environmental Requirements The following table...

Page 39: ...nge 0 5 C min according to NEBS Standard GR 63 CORE Forced Air Flow 250 LFM 55 C 131 F ambient temperature Relative humidity 5 to 90 5 to 90 Vibration 1 0G sine sweep 5 200 Hz 25 octaves min all 3 axis operating 5 20 Hz 0 01 g Hz 20 200 Hz 3 0 dB octave Random 5 20 Hz 1 m Sec Random 20 200 Hz 3 dB oct Shock Half sine 11 mSec 30 m Sec Blade level packaging Half sine 6 mSec at 180 m Sec Free Fall Bl...

Page 40: ...uirements The CPCI 6020 module requires a minimum air flow of 250 LFM when operating at a 55 C 131 F ambient temperature 2 6 Hardware Configuration To produce the desired configuration and ensure proper operation of the CPCI 6020 you may need to carry out certain hardware modifications before installing the module S ome hardware modifications are controlled through manual installation or removal o...

Page 41: ...oard Preparation Prior to installing any memory flash or PMC modules on the CPCI 6020 baseboard ensure that all jumpers that are user configurable are set properly To do this refer to Figure 2 1 or the board itself for the location of specific jumpers Set the jumpers according to the following descriptions Manually configured items on the baseboard include z Flash bank selection J24 z Harrier Powe...

Page 42: ...he CPCI 6020 For jumper locations see Figure 2 1 2 8 1 Flash Bank Selection The CPCI 6020 contains one bank of 32 MB 16 bit flash memory soldered on board Bank A and 1 MB of 16 bit socketed flash memory Bank B Bank A is 64 bits wide and Bank B is 16 bits wide Bank B contains the on board debugger and diagnostics PPCBug Figure 2 1 Header Locations and Jumper Settings J22 U19 U18 U31 1 3 J24 J20 J21...

Page 43: ...tion on PCI Bus B When a jumper is installed between pins 1 and 2 PCI Bus B will operate at 33 MHz regardless of whether the PMC is capable of 66 MHz This prevents the secondary Ethernet controller from being disabled if a 66 MHz capable PMC is installed The jumper pulls the M66EN signal low so the PMC can be aware that the bus is operating at 33 MHz 2 8 4 Enable Disable 12 V and 12 V Use This 0 1...

Page 44: ... A When a jumper is installed between pins 1 and 2 memory contents cannot be altered in the entire flash 2 8 7 Remote Switch This 0 1 inch 3 pin header J19 located on the CPCI 6020 allows you to connect a remote switch that performs the same function as front panel reset and abort switch The pin configuration is as follows 2 9 Hardware Installation The following sections discuss the installation o...

Page 45: ...wap chassis perform an operating system shutdown Turn the AC or DC power off and remove the AC cord or DC power lines from the system Remove the chassis or system cover s as necessary for access to the CompactPCI Damage of Circuits Electrostatic discharge and incorrect module installation and removal can damage circuits or shorten their life Before touching the module or electronic components make...

Page 46: ...CI 6020 6 Insert the four short phillips head screws provided with the PMC through the holes on the bottom side of the CPCI 6020 and the PMC front bezel and into rear standoffs Tighten the screws 7 Reinstall the CPCI 6020 assembly in its proper card slot Be sure the module is well seated in the backplane connectors Do not damage or bend connector pins 8 If the PMC module was installed in a non hot...

Page 47: ...cord or DC power lines from the system Remove the chassis or system cover s as necessary to access the compact PCI module 3 Carefully remove the CPCI 6020 from the CompactPCI card slot and place it on a clean and adequately protected working surface with connectors J1 through J5 facing you Board Damage Inserting or removing modules that are not HA capable with power applied may result in damage to...

Page 48: ... nad then reinstall the CPCI 6020 assembly in the proper card slot Check that the board is properly seated in the backplane connectors Take care not to damage or bend connector pins 2 12 Before You Install or Remove a Board Boards may be damaged if improperly installed or handled Please read and follow the guidelines in this section to protect your equipment Insert CompactFlash Damage of Circuits ...

Page 49: ... from bottom to top When inserting or removing a board in a slot adjacent to other boards use extra caution to avoid damage to the pins and components located on the primary or secondary sides of the boards 2 12 3 Understanding Hot Swap The PICMG 2 1 Hot Swap specification defines varying levels of hot swap A board that is compliant with the specification can be inserted and removed safely with sy...

Page 50: ... specification and are designed to meet the IEEE1101 10 standards Each lever type has a latching mechanism to prevent the lever from being opened accidentally You must press the lever release before you can open the lever Never force the lever If the lever does not open easily you may not have pressed firmly enough on the release If the lever does not close easily the board may not be properly sea...

Page 51: ...ons and colored card rails for slot purpose prior to installing a module Table 2 4 Slot Usage Indicators Card Rail Color Glyph Usage Tan none MXP Alarm Management Controller slot CPX Hot Swap Controller or Bridge slot Red MXP Fabric Switch Card slot CPX System Controller slot Black MXP Payload Card slot CPX Non system Controller or I O Card slot Preserve EMI Compliance To preserve compliance with ...

Page 52: ... explained in Before You Install or Remove a Board on page 47 Installation Procedure Hot swap compliant modules may be installed while the system is powered on If a module is not hot swap compliant you should remove power to the slot or system before installing the module See Understanding Hot Swap on page 48 for more information Signaling Requirements Ensure the backplane does not bus J3 J4 or J5...

Page 53: ...al and steady pressure as necessary to carefully slide the module into the card cage rail guides Stage 1 Continue to gently push until the prealignment guide pegs engage with the backplane connector Stage 2 and the injector levers make contact with the chassis rails Do not force the board into the backplane slot 4 Use the injector levers to seat the module in the slot by closing the levers until t...

Page 54: ...ule s captive screws at both ends of the front panel 2 Begin to remove your module by unlatching the ejector lever the lower lever on vertically mounted boards See Recognize Different Injector Ejector Lever Types on page 49 Do not remove the module immediately 3 Once the applications and operating system running on the board have stopped and it is safe to remove the board open both ejector levers ...

Page 55: ...llowing steps to ensure proper board operation 1 Before applying power ensure you configure the hardware properly for example jumper settings memory installation flash installation PMC installation and other hardware features 2 Check all connections and ensure the installation is complete cabling transition module connections if applicable 3 Once everything is verified power up the system When the...

Page 56: ...t be installed in a subrack system slot marked with a triangle symbol The CPCI 6020 provides seven peripheral slot clock outputs CLK0 CLK6 per CompactPCI specification 2 0 R2 1 Arbitration for the seven peripheral slot bus masters is provided by the CPCI 6020 On the CPCI 6020 baseboard the standard serial console port COM1 serves as the PPCBug debugger console port The firmware console should be s...

Page 57: ...or serial ports on CPCI 6020 boards After power up the baud rate can be changed using the PPCBug PF Port Format command via the command line interface Whatever the baud rate some type of hardware handshaking either XON OFF or via the RTS CTS line is desirable if the system supports it Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 58: ...PCI 6020 MCPTM 01 transition module and RAM500 memory modules can be found in Chapter 7 Transition Module Preparation and Installation and Chapter 6 RAM500 Memory Expansion Module respectively 3 2 CPCI 6020 Baseboard Layout The next figure illustrates the placement of the headers connectors and LED indicators on the CPCI 6020 Figure 3 1 Headers Connectors and LEDs Artisan Technology Group Quality ...

Page 59: ...ctors and the PMC front panel This section describes the baseboard connectors and LEDs 3 3 1 Front Panel Ethernet Port A 10BaseT 100BaseTx RJ 45 receptacle is located on the front panel of the CPCI 6202 to provide Ethernet I O The pin assignments for this connector are Figure 3 2 Front Panel Connectors and LEDs 10 100 BASE T USB1 USB0 COM1 ABT RST CPU FAIL HOLD PCI MEZZANINE CARD Table 3 1 Etherne...

Page 60: ...3 3 Front Panel USB ports There are two USB Series A receptacles located on the front panel of the CPCI 6020 The pin assignments are shown in the next tables 6 RD 7 AC Terminated 8 AC Terminated Table 3 1 Ethernet Connector Pin Assignments continued Pin Signal Table 3 2 COM1 Pin Assignments Signal Pin 1 DCD 2 RTS 3 GND 4 TXD 5 RXD 6 GND 7 CTS 8 DTR Table 3 3 USB Port 1 Pin Number Pin Name 1 USBVOU...

Page 61: ...etails of the BDFL bit 3 4 Connector Pin Assignments The following tables describe connectors available on the CPCI 6020 base board Note that the pin assignments for connectors J3 J4 and J5 apply to the transition module as well as the CPCI 6020 3 4 1 CompactPCI Bus Connectors The CPCI 6020 implements a 64 bit CompactPCI interface on connectors J1 and J2 Each of these connectors conform to the Com...

Page 62: ...21 20 AD12 GND VIO AD11 AD10 20 19 3 3 V AD15 AD14 GND AD13 19 18 SERR_L GND 3 3 V PAR CBE1_L 18 17 3 3 V No Connect SDONE No Connect SBO_L GND PERR_L 17 16 DEVSEL_L GND VIO STOP_L No Connect LOCK_L 16 15 3 3 V FRAME_L IRDY_L BD_SEL_L TRDY_L 15 12 14 KEY AREA 12 14 11 AD18 AD17 AD16 GND CBE2_L 11 10 AD21 GND 3 3 V AD20 AD19 10 9 CBE3_L IDSEL AD23 GND AD22 9 8 AD26 GND VIO AD25 AD24 8 7 AD30 AD29 A...

Page 63: ...GND No Connect FAL_L No Connect REQ5_L No Connect GNT5_L 15 14 AD35 AD34 AD33 GND AD32 14 13 AD38 GND VIO AD37 AD36 13 12 AD42 AD41 AD40 GND AD39 12 11 AD45 GND VIO AD44 AD43 11 10 AD49 AD48 AD47 GND AD46 10 9 AD52 GND VIO AD51 AD50 9 8 AD56 AD55 AD54 GND AD53 8 7 AD59 GND VIO AD58 AD57 7 6 AD63 AD62 AD61 GND AD60 6 5 CBE5_L 64EN L VIO CBE4_L PAR64 5 4 VIO No Connect BRSVP2B4 CBE7_L GND CBE6_L 4 3...

Page 64: ...CT_L RESERVED RESERVED TXD3 TXD4 15 14 3 3 V 3 3 V 3 3 V 5 V 5 V 14 13 PMCIO5 PMCIO4 PMCIO3 PMCIO2 PMCIO1 13 12 PMCIO10 PMCIO9 PMCIO8 PMCIO7 PMCIO6 12 11 PMCIO15 PMCIO14 PMCIO13 PMCIO12 PMCIO11 11 10 PMCIO20 PMCIO19 PMCIO18 PMCIO17 PMCIO16 10 9 PMCIO25 PMCIO24 PMCIO23 PMCIO22 PMCIO21 9 8 PMCIO30 PMCIO29 PMCIO28 PMCIO27 PMCIO26 8 7 PMCIO35 PMCIO34 PMCIO33 PMCIO32 PMCIO31 7 6 PMCIO40 PMCIO39 PMCIO38...

Page 65: ... D Row E Pin 25 AD36 AD35 AD34 AD33 AD32 25 24 AD40 AD39 AD38 GND AD37 24 23 AD45 AD44 AD43 AD42 AD41 23 22 AD49 3 3 V AD48 AD47 AD46 22 21 AD53 AD52 AD51 GND AD50 21 20 AD57 3 3 V AD56 AD55 AD54 20 19 AD61 AD60 AD59 GND AD58 19 18 CBE4 3 3 V PAR64 AD63 AD62 18 17 REQ64 CBE7 CBE6 GND CBE5 17 16 AD2 3 3 V AD1 AD0 ACK64 16 15 AD6 AD5 AD4 GND AD3 15 11 AD9 AD8 CBE0 GND AD7 11 10 AD13 5 0V AD12 AD11 A...

Page 66: ...18 17 RESERVED ENET1_T ENET2_T ENET1_R ENET2_R 17 16 RESERVED ENET1_T ENET2_T ENET1_R ENET2_R 16 15 RESERVED RESERVED RESERVED RESERVED RESERVED 15 14 RTSa CTSa RIa GND DTRa 14 13 DCDa 5 0 V RXDa DSRa TXDa 13 12 RTSb CTSb RIb 5 0V DTRb 12 11 DCDb GND RXDb DSRb TXDb 11 10 TR0_L WPROT_L RDATA_L HDSEL_L DSKCHG_L 10 9 MTR1_L DIR_L STEP_L WDATA_L WGATE_L 9 8 RESERVED INDEX_L MTR0_L DS1_L DS0_L 8 7 CS1F...

Page 67: ...data ENETn_T Low side of differential transmit data ENETn_T High side of differential transmit data Ethernet Ports 1 2 Floppy Disk TTL levels HDSEL_L Selects the top or bottom head INDEX_L Indicates the beginning of track INTRQ Drive the interrupt request IORDY Indicates the drive ready for I O KBAUXVCC Fused power for the keyboard and auxiliary device KBDDAT Clock for the PC AT or PS 2 keyboard K...

Page 68: ...e disk is write protected Table 3 12 J5 Signal Descriptions continued Signal Description Table 3 13 J8 and J27 Memory Mezzanine Connector Pin Pin Name Pin Name Pin Pin Pin Name Pin Name Pin 1 GND GND 2 73 DQ56 DQ57 74 3 DQ00 DQ01 4 75 DQ58 DQ59 76 5 DQ02 DQ03 6 77 DQ60 DQ61 78 7 DQ04 DQ05 8 79 GND GND 80 9 DQ06 DQ07 10 81 DQ62 DQ63 82 11 3 3 V 3 3 V 12 83 CKD00 CKD01 84 13 DQ08 DQ09 14 85 CKD02 CK...

Page 69: ... 122 51 3 3 V 3 3 V 52 123 3 3 V DQMB0 124 53 DQ40 DQ41 54 125 DQMB1 SCL 126 55 DQ42 DQ43 56 127 SDA A1_SPD 128 57 DQ44 DQ45 58 129 A0_SPD MEZZ1_L 130 59 DQ46 DQ47 60 131 MEZZ2_L GND 132 61 GND GND 62 133 GND SDRAMCLK1 134 63 DQ48 DQ49 64 135 SDRAMCLK3 3 3 V 136 137 SDRAMCLK4 SDRAMCLK2 138 67 DQ52 DQ53 68 139 GND GND 140 69 3 3 V 3 3 V 70 71 DQ54 DQ55 72 Table 3 13 J8 and J27 Memory Mezzanine Conn...

Page 70: ...45 VIO AD15 46 47 AD12 AD11 48 49 AD09 5 V 50 51 GND C BE0 52 53 AD06 AD05 54 55 AD04 GND 56 57 VIO AD03 58 59 AD02 AD01 60 61 AD00 5 V 62 63 GND REQ64 64 Table 3 15 J12 PMC Connector J12 Pin Assignments Pin Signal Signal Pin 1 12 V TRST 2 3 TMS TDO 4 5 TDI GND 6 7 GND PCI_RSVD 8 9 PCI_RSVD PCI_RSVD 10 11 MOT_RSVD 3 3 V 12 13 RST MOT_RSVD 14 15 3 3 V MOT_RSVD 16 17 PCI_RSVD GND 18 19 AD30 AD29 20 ...

Page 71: ...ND 44 45 AD14 AD13 46 47 M66EN AD10 48 49 AD08 3 3 V 50 51 AD07 REQB_L 52 53 3 3 V GNTB_L 54 55 MOT_RSVD GND 56 57 MOT_RSVD EREADY 58 59 GND NC RESETOUT_L 60 61 ACK64 3 3 V 62 63 GND NC MONARCH 64 Table 3 16 PMC Connector J13 Pin Assignments Pin Signal Signal Pin 1 PCI_RSVD GND 2 3 GND C BE7 4 5 C BE6 C BE5 6 7 C BE4 GND 8 9 VIO PAR64 10 11 AD63 AD62 12 13 AD61 GND 14 15 GND AD60 16 17 AD59 AD58 1...

Page 72: ...AD43 AD42 42 43 AD41 GND 44 45 GND AD40 46 47 AD39 AD38 48 49 AD37 GND 50 51 GND AD36 52 53 AD35 AD34 54 55 AD33 GND 56 57 VIO AD32 58 59 NC NC 60 61 NC GND 62 63 GND NC 64 Table 3 17 PMC Connector J14 Pin Assignments Pin Signal Signal Pin 1 PMCIO1 PMCIO2 2 3 PMCIO3 PMCIO4 4 5 PMCIO5 PMCIO6 6 7 PMCIO7 PMCIO8 8 9 PMCIO9 PMCIO10 10 11 PMCIO11 PMCIO12 12 13 PMCIO13 PMCIO14 14 15 PMCIO15 PMCIO16 16 Ta...

Page 73: ... 27 PMCIO27 PMCIO28 28 29 PMCIO29 PMCIO30 30 31 PMCIO31 PMCIO32 32 33 PMCIO33 PMCIO34 34 35 PMCIO35 PMCIO36 36 37 PMCIO37 PMCIO38 38 39 PMCIO39 PMCIO40 40 41 PMCIO41 PMCIO42 42 43 PMCIO43 PMCIO44 44 45 PMCIO45 PMCIO46 46 47 PMCIO47 PMCIO48 48 49 PMCIO49 PMCIO50 50 51 PMCIO51 PMCIO52 52 53 PMCIO53 PMCIO54 54 55 PMCIO55 PMCIO56 56 57 PMCIO57 PMCIO58 58 59 PMCIO59 PMCIO60 60 61 PMCIO61 PMCIO62 62 63 ...

Page 74: ...he PMC knows the bus is running at 33 MHz 3 4 9 Remote Switch Connector A 0 1 inch 3 pin header J19 located on the CPCI 6020 can be used to extend the front panel s Reset and Abort switches functions through the cables to a remote location 3 4 10 Flash Write Protect Enable Jumper A 0 1 inch 2 pin header J20 located on the CPCI 6020 enables write protect of bank A flash When a jumper is installed b...

Page 75: ...nk A Placing the jumper between pins 2 and 3 selects Xport 1 Flash Bank B The pin assignments for this header are as follows 3 4 13 RISCWatch Header The CPCI 6020 provides a standard 2x8 0 1 header for the RISCWatch interface The pin assignments for this header are as follows Table 3 22 J22 Harrier Power Up Configuration Header Pin Assignments Pin Signal Signal Pin Shunt On Shunt Off 1 XAD 20 term...

Page 76: ... 11 SRESET_L No Connect 12 13 CPURST_L VOID 14 15 CKSTPO_L GND 16 Table 3 24 J25 RISCWatch Header Pin Assignments continued Pin Signal Signal Pin Table 3 25 J28 Debug Connector Pin Signal Signal Pin 1 PA0 GND PA1 2 3 PA2 PA3 4 5 PA4 PA5 6 7 PA6 PA7 8 9 PA8 PA9 10 11 PA10 PA11 12 13 PA12 PA13 14 15 PA14 PA15 16 17 PA16 PA17 18 19 PA18 PA19 20 21 PA20 PA21 22 23 PA22 PA23 24 25 PA24 PA25 26 27 PA26 ...

Page 77: ...47 PD8 PD9 48 49 PD10 PD11 50 51 PD12 PD13 52 53 PD14 PD15 54 55 PD16 PD17 56 57 PD18 PD19 58 59 PA20 PD21 60 61 PD22 PD23 62 63 PD24 PD25 64 65 PD26 PD27 66 67 PD28 PD29 68 69 PD30 PD31 70 71 PD32 PD33 72 73 PD34 PD35 74 75 PD36 PD37 76 Table 3 25 J28 Debug Connector continued Pin Signal Signal Pin Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 78: ... PD48 PD49 88 89 PA50 PD51 90 91 PD52 PD53 92 93 PD54 PD55 94 95 PD56 PD57 96 97 PD58 PD59 98 99 PD60 PD61 100 101 PD62 PD63 102 103 PDPAR0 PDPAR1 104 105 PDPAR2 PDPAR3 106 107 PDPAR4 PDPAR5 108 109 PDPAR6 PDPAR7 110 111 Reserved Reserved 112 113 DPE_L DBDIS_L 114 Table 3 25 J28 Debug Connector continued Pin Signal Signal Pin Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURC...

Page 79: ...27 WT_L Reserved 128 129 GLOBAL_L Reserved 130 131 SHARED_L DBWO_L 132 133 AACK_L TS_L 134 135 ARTY_L XATS_L 136 137 DRTY_L TBST_L 138 139 TA_L Reserved 140 141 TEA_L Reserved 142 143 Reserved DBG_L 144 145 Reserved DBB_L 146 147 Reserved ABB_L 148 149 TCLK_OUT CPUGNT0_L 150 151 Reserved CPUREQ0_L 152 Table 3 25 J28 Debug Connector continued Pin Signal Signal Pin Artisan Technology Group Quality I...

Page 80: ...164 165 L2CLAIM_L TLBISYNC_L 166 167 Reserved TBEN 168 169 Reserved Reserved 170 171 Reserved GND Reserved 172 173 SRESET_L Reserved 174 175 HRESET_L NAPRUN 176 177 SRST1_L QREQ_L 178 179 SRESET0_D_L QACK_L 180 181 HRESET_L CPUTDO 182 183 GND CPUTDI 184 185 CPUCLK CPUTCK 186 187 CPUCLK CPUTMS 188 189 CPUCLK CPUTRST 190 Table 3 25 J28 Debug Connector continued Pin Signal Signal Pin Artisan Technolo...

Page 81: ...CompactPCI Single Board Computer Installation and Use 6806800A51C Controls LEDs and Connectors Mictor Debug Connector 80 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 82: ...ts and IDE A CompactFlash Type I II compatible socket residing on the IDE Bus is included onboard The floppy disk controller keyboard and mouse are supported only on the CPCI 6060 5E variants A parallel port which was available on the previous generation board has been eliminated in favor of routing the Ethernet ports to the backplane connectors The CPCI 6020 features two host bridges which allow ...

Page 83: ... Use 6806800A51C Functional Description Block Diagram 82 4 2 Block Diagram The following figure is a block diagram of the CPCI 6020 architecture Figure 4 1 Block Diagram Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 84: ...ary and secondary bus buffers The primary bus signalling voltage is tied to 5 V The secondary bus signalling voltage is tied to the CPCI Bus VIO so the CPCI 6020 is a universal board that may operate in a 3 3 V or 5 V chassis A CompactPCI Bus interface will support a maximum of seven CompactPCI cards loads per segment when operating at 33 MHz This CompactPCI Bus interface is compliant with the Com...

Page 85: ...s a primary and secondary EIDE interface for up to four EIDE devices and also supports ATAPI compliant devices The primary EIDE interface is routed to the CompactFLASH memory card The secondary EIDE interface is routed to the J5 User I O connector for interfacing to external EIDE devices Some Motorola HA chassis route the EIDE Bus across the backplane to the peripheral bay The secondary EIDE inter...

Page 86: ...esources The Harrier B ASIC bridges from the processor bus to PCI Bus B Other than the Harrier there are only two resources on the bus the secondary Ethernet controller and a PMC slot The PMC slot includes secondary arbitration and IDSEL signals as defined in the VITA 32 199x Processor PMC Standard which allows for two possible devices on the PMC on this bus segment PCI Bus B is compliant to PCI R...

Page 87: ...tion information for the 82551IT This is a 1 kilobit device organized as 64 16 bit words Table 4 1 Special Function Processor PMC Pins PrPMC Signal Pin Number Support PRESENT J11 7 The PRESENT signal from the slot is used in conjunction with M66EN to detect the presence of a 66 MHz capable PMC The state of this bit is readable in the external register set on Harrier A Xport channel 2 MONARCH J12 6...

Page 88: ...r data storage The external SRAMs are accessed through a dedicated 72 bit wide 64 bits of data and 8 bits of parity L2 cache port The MPC7410 processor can support up to 2 MB The L2 cache can operate in copyback or write through modes and supports system cache coherency through snooping Data parity generation and checking can be disabled by programming the processor L2 cache control registers acco...

Page 89: ...time The following table lists the default power up reset state of these pins for the CPCI 6020 The Select Option column indicates whether the power up setting can be changed by build option resistor or by jumper or if the setting is fixed and cannot be changed The default power up setting column indicates the default values of the standard CPCI 6020 product Default settings for jumper options ind...

Page 90: ...110 PPC to PCI clock ratio 3 1 111 Reserved XAD 11 10 Fixed A 01 B XX XCSR XPAT0 DW Harrier A Flash Bank A 16 bits wide Harrier B Flash Bank A not used XAD 9 Jumper on board A 1 B 0 XCSR XPAT0 RVEN Harrier A Flash Bank A is Reset Vector Harrier B has no flash XAD 8 7 Resistor A 01 B xx XCSR XPAT1 DW Harrier A Flash Bank B to 16 bit width Harrier B Flash Bank B not used XAD 6 Fixed A 1 B 0 XCSR XPA...

Page 91: ...the Harrier Application Specific Integrated Circuit ASIC Programmer s Reference Guide 4 7 ECC Memory Bus Resources The CPCI 6020 supports 2 GB of memory via four RAM500 mezzanine modules populated in the two memory connectors J7 and J28 There is no onboard memory The ECC protected memory mezzanines are distributed as separate sets one attached to each Harrier The CPCI 6020 supports a total of 1 GB...

Page 92: ...rs on CPCI 6020 has a separate Xport Bus The Xport Bus is the set of signals Harrier uses to control devices that have a simple static RAM style interface Such devices include flash NVRAM RTC and external registers A 60x bus slave and an Xport Bus master constitute the most significant blocks that make up Xport within Harrier The 60x bus slave has four address response ranges The Xport Bus master ...

Page 93: ...FFF00000 FFFFFFFF maps to Bank B When RVEN0 bit is set it maps to Bank A The default state uses Bank A for the reset vector Bank B may be selected by connecting the BANKB_SEL_L pin to GND Flash Bank B is not ECC protected 4 8 3 Harrier A Channel 2 NVRAM RTC External Register Set The Harrier A Xport 2 interface consists of the STMicroelectronics M48T37V This device provides 32 KB of nonvolatile sta...

Page 94: ...e CPCI 6020 provides two asynchronous serial interfaces UART0 and UART1 in the Harrier A provide the 16550 compatible UART controllers The UART0 port signals are wired to an RS 232 transceiver which interfaces to the front panel RJ 45 connector The UART0 port may optionally be wired to the backplane via J5 instead The UART1 port is wired to the J5 connector only An onboard 1 8432 MHz oscillator pr...

Page 95: ... Control and Status The Harrier ASIC contains a Miscellaneous Control and Status register that provides the CPCI 6020 with the board fail LED control PrPMC EREADY pin status board reset control and processor timebase enable control Refer to the Harrier Application Specific Integrated Circuit ASIC Programmer s Reference Guide for additional details 4 10 2 Clock Generator The CPCI 6020 clock generat...

Page 96: ...age for the processor Harriers and the L2 cache 1 8 V is generated using an onboard regulator through 3 3 V 4 10 4 Board Reset Logic A block diagram of the CPCI 6020 board reset logic is shown below The board reset logic is implemented in a programmable logic device PLD in order to provide maximum flexibility of the circuit design There are several potential sources of reset on the CPCI 6020 They ...

Page 97: ... Harrier B are tied to those of Harrier A respectively The AUXRST_ and RSTSW_ inputs of Harrier B are held inactive The RSTOUT_ HRST0_ and SRST0_ outputs of Harrier B are not connected The watchdog timers of Harrier B do not generate reset The following table shows which devices are affected by various reset sources Figure 4 2 Reset Block Diagram Table 4 6 Reset Sources and Devices Affected Device...

Page 98: ... accidental activation The ABORT signal is connected to the Harrier Abort Switch ABTSW_L input and generates an MPIC internal interrupt The RESET signal is connected to the Harrier Reset Switch RSTSW_L input which will generate a Harrier Reset Out which is ORed with the board reset logic Each signal is debounced in the Harrier ASIC Software Hard Reset Harrier RSTOUT PBC Port 92 Software Hard Reset...

Page 99: ...ction process of the full hot swap system model defined in the CompactPCI Hot Swap Specification This hardware supports the hot swap of peripheral boards in standardized non high availability chassis Hot swapping of the CPCI 6020 the system controller itself is not defined in the CompactPCI specifications A description of CPCI 6020 support for system slot hot swapping is in the following high avai...

Page 100: ... this manner the bus may be made quiescent in preparation for a transfer of control from the CPCI 6020 to the bridge board that bridges the remote domain down to the local CompactPCI Bus 4 12 4 Secondary Bus Tri Stating When the CPCI 6020 is taken offline by the bridge board from the remote domain its 21154 must be disabled to prevent it from responding to backplane transactions The 21154 is desig...

Page 101: ...ales representative for more information on the transition board option The second Ethernet interface is routed only to the J5 connector for Ethernet connection on the CPCI 6020 MCPTM 01 The Ethernet Station Addresses are determined by the CPCI 6020 and are not affected by the CPCI 6020 MCPTM 01 4 15 Hot Swap Support The CPCI 6020 MCPTM 01 is considered to be part of the CPCI 6020 Therefore the CP...

Page 102: ...CC on CPCI 6020 Since the Z85230 does not have all modem control lines a Z8536 CIO is used to provide the missing modem lines All modem control lines from the ESCC are multiplexed de multiplexed through J3 by the P2MX function due to I O pin limitations This hardware function is transparent to software The block diagram for the signal multiplexing on the CPCI 6020 MCPTM 01 is shown in the followin...

Page 103: ...MHz bit rate Sixteen time slots are defined and allocated as follows Table 4 7 Multiplexing Sequence of the IOMX Function MXDO From CPCI 6020 MXDI From CPCI 6020 MCPTM 01 TIME SLOT SIGNAL NAME TIME SLOT SIGNAL NAME 0 RTS3 0 CTS3 1 DTR3 1 DSR3 2 LLB3 2 DCD3 3 RLB3 3 TM3 4 RTS4 4 RI3 5 DTR4 5 CTS4 6 LLB4 6 DSR4 7 RLB4 7 DCD4 8 Reserved 8 TM4 9 Reserved 9 RI4 10 Reserved 10 Reserved 11 Reserved 11 Re...

Page 104: ...rds which contain all the circuitry needed to convert a TTL level port to the standard voltage levels needed by various industry standard serial interfaces such as EIA 232 EIA 530 etc 4 21 PMC Interface Module PIM The CPCI 6020 MCPTM 01 provides additional I O capabilities for the CPCI 6020 There are two distinct groups of I O passed from the CPCI 6020 to the CPCI 6020 MCPTM 01 through the Compact...

Page 105: ... the VITA36 standard is identical to the single wide PMC form factor with the following differences z Shorter by 80 mm z Deletes the 5 V and 3 3 V keys z Pn1 and Pn3 are deleted The 80 mm is cut out of the middle of the PIM This means that it preserves all the features near the front edge of the board as well as the features close to the back of the board without keeping the complete middle portio...

Page 106: ...ds the host I O module may be reused If possible optional host I O routed to the host I O connector will be terminated in such a fashion that the host does not incorrectly determine that a device is connected to that I O when no module is present This termination must not interfere with normal operation of the I O when a module is present 4 25 Speaker Port The 2 pin header provides connection to a...

Page 107: ...0 CompactPCI Single Board Computer Installation and Use 6806800A51C Functional Description Mouse and Keyboard Port 106 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 108: ...tics User s Manual listed in Appendix A Related Documentation 5 2 PPCBug Basics The debug firmware PPCBug is a powerful evaluation and debugging tool that provides facilities for loading and executing user programs under complete operator control for system evaluation PPCBug provides a high degree of functionality user friendliness portability and ease of maintenance Furthermore PPCBug is portable...

Page 109: ...M tunable value For example a system containing 64 MB 04000000 of read write memory using 1 MB of memory will place the PPCBug memory page at locations 03F00000 to 03FFFFFF In addition PPCBug will use certain parts of low memory typically from 0 to 4000 for exception vector table data Avoid using any predefined address space in order to alleviate writing over any existing firmware code or data 5 4...

Page 110: ...le host ports and initializes the appropriate devices PC16550 GD54xx Z85C230 21 Displays the debugger s copyright message 22 Displays any hardware initialization errors that may have occurred 23 Checksums the debugger object and displays a warning message if the checksum failed to verify 24 Displays the amount of local read write memory found 25 Verifies the configuration data that is resident in ...

Page 111: ...nt is encountered during execution of the user program However the user program can return to the debugger by means of the System Call Handler routine RETURN For more about this refer to the GD GO and GT command descriptions in the PPCBug Firmware Package User s Manual A debugger command is made up of the following parts z The command name either uppercase or lowercase e g MD or md z Any required ...

Page 112: ...Data CSAR PCI Configuration Space READ Access CSAW PCI Configuration Space WRITE Access DC Data Conversion and Expression Evaluation DS Disassembler DU Dump S Records ECHO Echo String ENV Set Environment to Bug Operating System FORK Fork Idle MPU at Address FORKWR Fork Idle MPU with Registers G Alias for GO Command GD Go Direct Ignore Breakpoints GEVBOOT Global Environment Variable Boot Bootstrap ...

Page 113: ...ting MAR Macro Load MAW Macro Save MD Memory Display MENU System Menu MM Memory Modify MMD Memory Map Diagnostic MMGR Access Memory Manager MS Memory Set MW Memory Write NAB Network Automatic Bootstrap Operating System NAP Nap MPU NBH Network Bootstrap Operating System and Halt NBO Network Bootstrap Operating System NIOC Network I O Control NIOP Network I O Physical NIOT I O Teach for Configuring ...

Page 114: ...pheral Bay PWRON Power On PCI Slot Power Supply Peripheral Bay RB ROM Bootstrap Operating System RD Register Display REMOTE Connect the Remote Modem to CSO RESET Cold Warm Reset RL Read Loop RM Register Modify RS Register Set RUN MPU Execution Status SD Switch Directories SET Set Time and Date SROM SROM Examine Modify SYM Attach Symbol Table SYMS Display Symbol Table T Trace TA Terminal Attach TIM...

Page 115: ...ach test group Refer to the PPCBug Diagnostics Manual for complete descriptions of the diagnostic routines and instructions on how to invoke them You may enter command names in either uppercase or lowercase Some diagnostics depend on restart defaults that are set up only in a particular restart mode Refer to the documentation on a particular diagnostic for the correct mode Some test groups have su...

Page 116: ... EIDE Tests ISABRDGE PCI ISA Bridge Tests KBD8730x PC8730x Keyboard Mouse Tests L2CACHE Level 2 Cache Tests NCR NCR 53C8xx SCSI 2 I O Processor Tests PAR8730x PC8730x Parallel Port Test PCIBUS Generic PCI PMC Slot Test RAM Random Access Memory Tests RTC MK48Txx Real Time Clock Tests SCC Serial Communications Controller Tests UART Serial Input Output UART Tests VGA54xx Video Graphics Tests Z8536 Zi...

Page 117: ...CPCI 6020 CompactPCI Single Board Computer Installation and Use 6806800A51C Firmware Diagnostic Tests 116 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 118: ...r memory mezzanine site are allowed one bottom and one top If only one module is used the RAM500 module with the top configuration is recommended 6 2 RAM500 Description The RAM500 is a memory expansion module that is used on the CPCI 6020 Single Board Computer as well as other Motorola products The RAM500 is based on a single memory mezzanine board design with the flexibility of being populated wi...

Page 119: ...top of the CPCI 6020 for on board memory capability To upgrade or install a RAM500 module follow these steps 1 Attach an ESD strap to your wrist Attach the other end of the ESD strap to the chassis as a ground The ESD strap must be secured to your wrist and to ground throughout the procedure 2 Perform an operating system shutdown Turn the AC or DC power off and remove the AC cord or DC power lines...

Page 120: ...reconnect the system to the AC or DC power source and turn the equipment power on 6 4 Features The following table lists the features of the RAM500 memory expansion module 6 4 1 SROM The RAM500 memory expansion module contains a single 3 3 V 256 x 8 Serial EEPROM device AT24C02 The Serial EEPROM provides Serial Presence Detect SPD storage of the module memory subsystem configuration The RAM500 SPD...

Page 121: ...p RAM500 module has only one connector since it needs to mate only with the RAM500 module directly underneath it and because an added connector on a tandem RAM500 configuration would exceed the height limitations in some backplanes If only one RAM500 module is being used a top module single connector configuration is used A 4H plug and receptacle are used on both boards to provide a 4 millimeter s...

Page 122: ...37 DQ28 DQ29 38 39 DQ30 DQ31 40 41 GND GND 42 43 DQ32 DQ33 44 45 DQ34 DQ35 46 47 DQ36 DQ37 48 49 DQ38 DQ39 50 51 3 3 V 3 3 V 52 53 DQ40 DQ41 54 55 DQ42 DQ43 56 57 DQ44 DQ45 58 59 DQ46 DQ47 60 61 GND GND 62 63 DQ48 DQ49 64 65 DQ50 DQ51 66 67 DQ52 DQ53 68 69 3 3 V 3 3 V 70 71 DQ54 DQ55 72 73 DQ56 DQ57 74 75 DQ58 DQ59 76 77 DQ60 DQ61 78 79 GND GND 80 81 DQ62 DQ63 82 Table 6 3 RAM500 Bottom Side Conne...

Page 123: ...5 CKD02 CKD03 86 87 CKD04 CKD05 88 89 3 3 V 3 3 V 90 91 CKD06 CKD07 92 93 BA1 BA0 94 95 A12 A11 96 97 A10 A09 98 99 GND GND 100 101 A08 A07 102 103 A06 A05 104 105 A04 A03 106 107 A02 A01 108 109 3 3 V 3 3 V 110 111 A00 CS_C0_L 112 113 CS_E0_L GND 114 115 CS_C1_L CS_E1_L 116 117 WE_L RAS_L 118 119 GND GND 120 121 CAS_L 3 3 V 122 123 3 3 V DQMB0 124 125 DQMB1 SCL 126 127 SDA A1_SPD 128 129 A0_SPD M...

Page 124: ...MB of memory The pin assignments for this connector are as follows Table 6 4 RAM500 Top Side Connector J1 Pin Assignments Pin Signal Signal Pin 1 GND GND 2 3 DQ00 DQ01 4 5 DQ02 DQ03 6 7 DQ04 DQ05 8 9 DQ06 DQ07 10 11 3 3 V 3 3 V 12 13 DQ08 DQ09 14 15 DQ10 DQ11 16 17 DQ12 DQ13 18 19 DQ14 DQ15 20 21 GND GND 22 23 DQ16 DQ17 24 25 DQ18 DQ19 26 27 DQ20 DQ21 28 29 DQ22 DQ23 30 31 3 3 V 3 3 V 32 33 DQ24 D...

Page 125: ...5 CKD02 CKD03 86 87 CKD04 CKD05 88 89 3 3 V 3 3 V 90 91 CKD06 CKD07 92 93 BA1 BA0 94 95 A12 A11 96 97 A10 A09 98 99 GND GND 100 101 A08 A07 102 103 A06 A05 104 105 A04 A03 106 107 A02 A01 108 109 3 3 V 3 3 V 110 111 A00 CS_E0_L 112 113 GND 114 115 CS_E1_L 116 117 WE_L RAS_L 118 119 GND GND 120 121 CAS_L 3 3 V 122 123 3 3 V DQMB1 124 125 SCL 126 127 SDA 128 129 A1_SPD MEZZ2_L 130 Table 6 4 RAM500 T...

Page 126: ...ates 6 6 RAM500 Programming Issues The RAM500 contains no user programmable registers other than the Serial Presence Detect SPD Data 131 GND 132 133 GND SDRAMCLK3 134 135 3 3 V 136 137 SDRAMCLK4 138 139 GND GND 140 Table 6 4 RAM500 Top Side Connector J1 Pin Assignments continued Pin Signal Signal Pin Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 127: ...pactPCI Single Board Computer Installation and Use 6806800A51C RAM500 Memory Expansion Module RAM500 Programming Issues 126 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 128: ...he CPCI 6020 MCPTM 01 7 2 General Description The CPCI 6020 MCPTM 01 provides additional I O capabilities to the CPCI 6020 board The CPCI 6020 MCPTM 01 is installed directly in the CompactPCI backplane in the rear transition board bay of the chassis and interfaces with the CPCI 6020 board through the J3 and J5 connectors It includes the following features z Secondary EIDE interface via J5 user I O...

Page 129: ...5 connectors For a detailed description of the PMC Interface Module see PMC Interface Module PIM on page 100 Besides these CPCI 6020 MCPTM 01 supports two synchronous Serial Interface Modules SIMs Figure 7 1 Block Diagram EIDE Control Data Data 10 100Tx 10 100Tx COM 1 COM 3 COM 4 KB MS Speaker EIDE Connector Floppy Connector PIM Site User I O J3 Connector User I O J5 Connector IOMX Function SSC Mo...

Page 130: ...allation and Use 6806800A51C 129 7 2 1 Component Layout The next figure shows the layout of the CPC 6020 MCPTM 01 major components Figure 7 2 Component Layout J21 J11 J18 J15 J10 J14 J7 J6 J2 J8 J12 J1 J9 J13 J19 J16 J17 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 131: ...anel Connectors 130 7 2 2 Rear Panel Connectors The next figure shows the location of all connectors and the PMC cutout of the CPCI 6020 MCPTM 01 Figure 7 3 Rear Panel Connectors Cut outs PMC I O Module COM1 ENET 1 ENET 2 Serial 3 4 KB MS Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 132: ...ides two 16550 compatible asynchronous serial interfaces COM1 and COM2 The COM1 port signals are wired to the front panel RJ 45 connector but it may optionally be wired to the backplane via J5 instead The COM2 port is wired to the J5 connector only COM1 is routed to an RJ 45 connector located at the rear panel of the CPCI 6020 MCPTM 01 COM2 can be accessed by a planar 9 pin header on the transitio...

Page 133: ...synchronous serial ports Serial Ports 3 and 4 are configured through a combination of serial interface module SIM selection and jumper settings A SIM is a small plug in printed circuit board that converts the TTL level synchronous or asynchronous port signals to industry standard voltage levels used by the ports The SIM contains the receiver and transmitter circuits for converting the input and ou...

Page 134: ...ext figures illustrate the CPCI 6020 baseboard and CPCI 6020 MCPTM 01 transition module with the interconnections and jumper settings for DCE DTE configuration on each serial port 7 4 3 Serial Interface Module Circuitry Each Serial Interface Module SIM has a 60 pin connector that provides all signal and power connections to the CPCI 6020 MCPTM 01 transition module All TTL level signals with the ex...

Page 135: ...he MC145406 ICs convert the EIA 232 D input signals to TTL voltage levels which are sent to the CPCI 6020 For all port interfaces the SIMs support the transmitter signal element timing as either input or output signals The MC145406 transceiver IC requires a series diode on the 12 V supply and a clamp diode to logic ground on the 12 V supply The diodes are located on the transition module rather th...

Page 136: ...20 MCPTM 01 Figure 7 5 EIA 232 D DCE Ports 3 and 4 Configuration TXD RTS RXD CTS RTXC TRXC EIA 232 D DCE SIM DSR DTR LLB RLB DCD RI TM 7 24 21 20 19 17 6 2 4 1 14 3 16 23 5 Z85230 SCC Z8536 CIO HD 26 J3 MX RXD CTS TXD RTS DTR TXC RXC ETXC DCD TM RI DSR RL LL GND J17 J16 3 2 1 Transition Module CPCI 6020 MCPTM 01 CPCI 6020 COM3 COM4 J1 J1 27 29 26 28 44 39 41 48 32 49 46 30 45 42 31 Artisan Technol...

Page 137: ...ther DCE or DTE The SIMs plug into connectors J12 COM3 and J13 COM4 on the CPCI 6020 MCPTM 01 Refer to Figure 7 4 on page 133 for connector and header locations Install the SIMs on the CPCI 6020 MCPTM 01 transition module using the following procedure Figure 7 6 EIA 232 D DTE Ports 3 and 4 Configuration TXD RTS RXD CTS RTXC TRXC EIA 232 D DTE SIM DSR DTR LLB RLB DCD RI TM 19 17 20 21 7 24 6 1 3 2 ...

Page 138: ...ign the SIM so that P1 on the SIM align with the appropriate SIM connector J12 for COM3 and J13 for COM4 on the transition module Note the position of the alignment key on P1 Refer to the following figure 2 Place the SIM onto the transition module SIM connector making sure that the mounting holes also align with the standoffs on the transition module as shown in the following figure SIM Alignment ...

Page 139: ... ESD strap to the chassis as a ground The ESD strap must be secured to your wrist and to ground throughout the procedure 2 Perform an operating system shutdown Turn the AC or DC power off and remove the AC cord or DC power lines from the system 3 Remove chassis or system cover s as necessary for access to the CompactPCI 4 Carefully remove the transition module from its CompactPCI card slot and lay...

Page 140: ...ur short Phillips screws provided with the PIM through the holes on the bottom side of the transition module into the PIM front bezel and rear standoffs Tighten the screws 8 With the CPCI 6020 MCPTM 01 in the correct vertical position that matches the pin positioning of the backplane carefully slide the transition module into the appropriate slot and seat tightly into the backplane 9 Secure in pla...

Page 141: ...tem Remove the chassis or system cover s as necessary for access to the chassis backplane 3 With the CPCI 6020 MCPTM 01 in the correct vertical position that matches the pin positioning of the backplane carefully slide the transition module into the appropriate slot and seat tightly into the backplane 4 Secure in place with the screws provided making good contact with the transverse mounting rails...

Page 142: ...Cables The connectors on the CPCI 6020 MCPTM 01 transition module are listed in the next table The port connectors are located on the front panel and the top side of the transition module which is shown in Figure 7 2 Refer to Table 7 3 on page 142 for a list of the cables and Connector Pin Assignments on page 143 for connector pinout information Table 7 2 Rear Transition Module Connectors Headers ...

Page 143: ...with CPCI 6020 MCPTM 01 Keyboard mouse Y adapter cable Motorola Part Number 30 W2309E01A User supplied 40 line flat ribbon cable with 40 pin header connectors for EIDE drives User supplied 34 line flat ribbon cable with 34 pin header connectors for floppy drive CA 8205E Y adapter cable HD 50 male connector to two HD 26 female connectors User supplied 2 line cable with 2 pin header connector for sp...

Page 144: ...ector routes the I O signals for the two COM ports the EIDE secondary port the keyboard the mouse the two USB ports not implemented on the CPCI 6020 MCPTM 01 but related signals are routed to the host I O connector of the PMC I O interface and the two Ethernet ports The pinouts for this connector are identical to those on the corresponding J5 connector on the CPCI 6020 and are described in Chapter...

Page 145: ...rved 38 39 Reserved Reserved 40 41 Reserved 3 3 V 42 43 Reserved UDATA0 44 45 GND UDATA0 46 47 UVCC1 UVCC0 48 49 UDATA1 GND 50 51 UDATA1 OUT_RI 52 53 5 V OUT_DCD 54 55 OUT_DTR OUT_DSR 56 57 OUT_CTS 3 3 V 58 59 OUT_RTS OUT_RXD 60 61 12 V OUT_TXD 62 63 I2C_CLK I2C_DAT 64 Table 7 5 PMC I O Module PMC I O Connector Pin Assignments Pin Signal Signal Pin 1 PMC IO1 PMC IO2 2 3 PMC IO3 PMC IO4 4 5 PMC IO5...

Page 146: ...2 33 PMC IO33 PMC IO34 34 35 PMC IO35 PMC IO36 36 37 PMC IO37 PMC IO38 38 39 PMC IO39 PMC IO40 40 41 PMC IO41 PMC IO42 42 43 PMC IO43 PMC IO44 44 45 PMC IO45 PMC IO46 46 47 PMC IO47 PMC IO48 48 49 PMC IO49 PMC IO50 50 51 PMC IO51 PMC IO52 52 53 PMC IO53 PMC IO54 54 55 PMC IO55 PMC IO56 56 57 PMC IO57 PMC IO58 58 59 PMC IO59 PMC IO60 60 61 PMC IO61 PMC IO62 62 63 PMC IO63 PMC IO64 64 Table 7 5 PMC ...

Page 147: ...ohm resistors be installed on the CPCI 6020 The pin assignments for these connectors are as follows 7 9 4 COM1 Connector An RJ 45 connector is located on the panel of the CPCI 6020 MCPTM 01 to provide the interface to the COM1 serial port This port is configured as DCE The pin assignments for this connector are as follows Table 7 6 10BaseT 100BaseTx Connector Pin Assignments Pin Signal 1 TD 2 TD 3...

Page 148: ...to the secondary EIDE port The pin assignments for this header are as follows Table 7 8 COM2 Header Pin Assignments Pin Signal Signal Pin 1 DCD DSR 2 3 RXD RTS 4 5 TXD CTS 6 7 DTR RI 8 9 GND VOID Key 10 Table 7 9 EIDE Header Pin Assignments Pin Signal Signal Pin 1 DRESET_L GND 2 3 DD7 DD8 4 5 DD6 DD9 6 7 DD5 DD10 8 9 DD4 DD11 10 11 DD3 DD12 12 13 DD2 DD13 14 15 DD1 DD14 16 17 DD0 DD15 18 19 GND No...

Page 149: ... external device powered from this connector must draw no more than 200mA The pin assignments are listed in the following table 39 No Connect GND 40 Table 7 9 EIDE Header Pin Assignments continued Pin Signal Signal Pin Table 7 10 Floppy Header Pin Assignments Pin Signal Signal Pin 1 GND No Connect 2 3 GND No Connect 4 5 GND No Connect 6 7 No Connect INDEX_L 8 9 GND MTR0_L 10 11 GND DS1_L 12 13 No ...

Page 150: ...OM4 is provided by a 50 pin female connector The connector shield for the port is tied to chassis ground The pin assignments and signal mnemonics are listed in the following table Pin assignments for this connector change depending on which SIM is plugged into the connector 4 No Connect Table 7 11 5Vdc Power Connector continued Pin Signal Table 7 12 Keyboard Mouse Connector Pin Assignments Pin Sig...

Page 151: ... SP3_P13 SP4_P13 37 13 SP3_P14 SP4_P14 38 14 TXCI3 TXCI4 39 15 SP3_P16 SP4_P16 40 16 RXCI3 RXCI4 41 17 LLB3 LLB4 42 18 SP3_P19 SP4_P19 43 19 DTR3 DTR4 44 20 RLB3 RLB4 45 21 RI3 RI4 46 22 SP3_P23 SP4_P23 47 23 TXCO3 TXCO4 48 24 TM3 TM4 49 25 SP3_P26 SP4_P26 50 Table 7 13 Sync Async Serial Connector Pin Assignments continued Pin Signal Signal Pin Table 7 14 Speaker Output Connector Pin Assignments P...

Page 152: ...t additional information about CNFG and ENV that is specific to the PPCBug debugger along with the parameters that can be configured with the ENV command 8 2 CNFG Configure Board Information Use this command to display and configure the Board Information Block which is stored in the NVRAM The Board Information Block lists details of your specific board such as the Board Serial Number the Board Ide...

Page 153: ... or configure interactively all PPCBug operational parameters that are kept in Non Volatile RAM NVRAM Refer to the PPCBug Firmware Package User s Manual for a description of the use of ENV Listed and described next are the parameters that you can configure using ENV The default values shown were those in effect when this publication went to print 8 4 Configuring the PPCBug Parameters You can confi...

Page 154: ...upported controllers Default N Accesses will not be made to the VMEbus to determine the presence of supported controllers Y NVRAM Prep partition header space is initialized automatically during board initialization but only if the PReP partition fails a sanity check Default N NVRAM header space will not be initialized automatically during board initialization Y Enable PReP style network booting sa...

Page 155: ...time value is from 0 255 seconds Default 5 seconds Auto Boot Enable Y N N Auto Boot at power up only Y N N Auto Boot Scan Enable Y N Y Auto Boot Scan Device Type List FDISK CDROM TAPE HDISK Y Give boot priority to devices defined in the fw boot path global environment variable GEV N Do not give boot priority to devices listed in the fw boot path GEV Default Y Give boot priority to devices defined ...

Page 156: ... in seconds that the Autoboot sequence will delay before starting the boot The purpose for the delay is to allow you the option of stopping the boot by use of the BREAK key The time value is from 0 255 seconds Default 7 seconds Auto Boot Default String NULL for an empty string You may specify a string filename which is passed on to the code being booted The maximum length of this string is 16 char...

Page 157: ... The failover takes place when the primary reports a hard error Refer to the PPCBug Firmware Package User s Manual for a listing of network controller modules currently supported b the PPCBug Network Auto Boot Device LUN 00 Refer to the PPCBug Firmware Package User s Manual for a listing of network controller modules currently supported by PPCBug Default 00 Network Auto Boot Abort Delay 5 The time...

Page 158: ... exceed 128 bytes in size The setting of this ENV pointer determines their location If you have used the same space for your own program information or commands they will be overwritten and lost You can relocate the network interface configuration parameters in this space by using the ENV command to change the Network Auto Boot Configuration Parameters Offset from its default of 00001000 to the va...

Page 159: ...ilable banks of DRAM memory ROM Bank A Access Speed ns 150 This is the access speed in nanoseconds of the device ROM Bank B Access Speed ns 120 This is the access speed in nanoseconds of the device DRAM Parity Enable On Detection Always Never O A N 0 The parameter above also applies to enabling ECC for DRAM L2 Cache Parity Enable On Detection Always Never O A N 0 Y If selftest fails do not autoboo...

Page 160: ... progressed before stalling The codes are enabled by an ENV parameter Serial Startup Code LF Enable Y N N A line feed can be inserted after each code is displayed to prevent it from being overwritten by the next code This is also enabled by an ENV parameter A list of LED serial codes is included in the section on MPU Hardware and Firmware Initialization in Chapter 1 of the PPCBug Firmware Package ...

Page 161: ... be typed just as you enter the commands from the command line The string NULL on a new line terminates the command line entries All BUG commands except for the following may be used within the command buffer DU ECHO LO TA VE Interactive editing of the startup command buffer is not supported If changes are needed to an existing set of startup commands a new set of commands with changes must be ree...

Page 162: ...formation refer to the following table for manufacturers data sheets or users manuals As an additional help a source for the listed document is also provided Please note that in many cases the information is preliminary and the revision levels of the documents are subject to change without notice Table A 1 Embedded Communications Computing Documents Document Title Publication Number CPCI 6020 Comp...

Page 163: ...to PCI Bridge 21554 htm 1 8 Volt StrataFlash Memory 1 8 V StrataFlash Memory STMicroelectronics http www st com stonline 48T37V CMOS 8K x 8 TIMEKEEPERTM SRAM Data Sheet 48T37V Winbond Electronics Corporation http www winbond com PC97317 ICL VUL Super I OTM Enhanced Sidewinder Lite Floppy Disk Controller Keyboard Controller Real Time Clock Dual UARTs IEEE 1284 Parallel Port and IDE Interface PC9731...

Page 164: ...e Access with Collision Detection CSMA CD Access Method and Physical Layer Specifications Global Engineering Documents http global ihs com index cfm for publications This document can also be obtained through the national standards body of member countries ISO IEC 8802 3 ANSI Small Computer System Interface 2 SCSI 2 Draft Document Global Engineering Documents http global ihs com index cfm for publ...

Page 165: ...20 CompactPCI Single Board Computer Installation and Use 6806800A51C Related Documentation Related Specifications 164 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 166: ...Auto Boot Default String 155 Auto Boot Device LUN 155 Auto Boot Enable 154 Auto Boot Partition Number 155 Auto Boot Scan Device Type List 154 Auto Boot Scan Enable 154 Auto Initialize of NVRAM Header Enable 153 Bug AST or System mode 152 DRAM Parity Enable 158 DRAM Speed in NANO Seconds 158 Field Service Menu Enable 153 Firmware Command Buffer 159 Firmware Command Buffer Delay 159 Firmware Command...

Page 167: ...sor bus 75 O ordering product 33 P parameters configure PPCBug 152 PBC EIDE interface 84 PCI Bus A resources 83 PCI Bus B 85 PCI Bus B resources 85 PCI buses 83 PIM installation 138 pin assignments 5Vdc power connector CPCI 6020 MCPTM 01 148 COM1 connector CPCI 6020 MCPTM 01 146 COM2 header CPCI 6020 MCPTM 01 147 CPCI 6020 MCPTM 01 PIM connector 143 EIDE header CPCI 6020 MCPTM 01 147 Ethernet conn...

Page 168: ...500 as memory module 117 serial ports 84 COM1 COM2 131 COM3 COM4 132 SIM circuitry described 133 installation procedure CPCI 6020 MCPTM 01 136 part numbers 132 SPD RAM500 118 120 speaker output header CPCI 6020 MCPTM 01 150 specification compliancy 32 specifications CPCI 6020 37 SROM RAM500 119 standard compliancy 32 startup overview 36 sync async serial ports CPCI 6020 MCPTM 01 149 synchronous se...

Page 169: ...CPCI 6020 CompactPCI Single Board Computer Installation and Use 6806800A51C 168 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 170: ...l service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE INSPECTION Remotely inspect equipment before purchasing with our interactive website at www instraview com LOOKING FOR MORE INFORMATION Visit us on the web at www artisantg com for more information on ...

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