Program and Data Memory
MOTOROLA
Technical Summary
2-5
This memory bank will operate with zero wait state access while the 56F8346 is running at
60MHz and can be disabled by removing the jumpers at JG6.
Figure 2-2. Schematic Diagram of the External CS1/CS2 Memory Interface
56F8346
GS72116
A0-A16
D0-D15
RD
WR
A0-A16
DQ0-DQ15
OE
WE
CE
JG6
Jumper Pin 1-2:
Enable SRAM Low Byte
DS/CS1
PD0/CS2
1
3
2
4
LB
HB
Jumper Pin 3-4:
Enable SRAM High Byte
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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