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Mostek z80, Technical Manual

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Summary of Contents for z80

Page 1: ...MOSTEK CO Z80 Technical Manual MK3881 PARALLEL I O CONTROLLER...

Page 2: ...g 13 5 2 Input Mode Timing 13 5 3 Bidirectional Mode Timing 14 5 4 Control Mode 14 6 0 Interrupt Control 15 7 0 Applications 17 7 1 Interrupt Daisy Chain 17 7 2 I O Device Interface 18 7 3 Control Int...

Page 3: ...andshake Daisy chain priority interrupt logic included to provide for automatic interrupt vectoring without external logic Eight outputs are capable of driving Darlington transistors All inputs and ou...

Page 4: ......

Page 5: ...L CONTROL LOGIC CPU INTERFACE 7 H DATA BUS 4 PIO CONTROL LINES CPU BUS I O c INTERNAL BUS INTERRUPT CONTROL PORT A I O a E a c HANDSHAKE PORT B I O y DATA OR CONTROL HANDSHAKE PERIPHERAL INTERFACE INT...

Page 6: ...ority interrupt structures The priority of any device is determined by its physical location in a daisy chain configuration Two lines are provided in each PIO to form this daisy chain The device close...

Page 7: ...ard Z 80 system clock to synchronize certain signals intemally This is a single phase clock Ml Machine Cycle One Signal from CPU input active low This signal from the CPU is used as a sync pulse to co...

Page 8: ...utput register is gated onto Port A bidirectional data bus The positive edge of the strobe acknowledges the receipt of the data 4 Control mode The strobe is inhibited internally A RDY Register A Ready...

Page 9: ...IP ENABLE MT lORQ RD H5V GND 1 INTERRUPT CONTROL INT INT ENABLE IN INT ENABLE OUT 39 38 37 36 JTT 35 26 11 25 23 24 22 Z80 PIO MK 3881 15 14 13 12 10 18 16 27 28 29 30 31 32 33 34 21 17 B RDY BSTB POR...

Page 10: ...1 9 t 9...

Page 11: ...eset state it is held there until the PIO receives a control word from the CPU 4 2 LOADING THE INTERRUPT VECTOR The PIO has been designed to operate with the Z80 CPU using the mode 2 interrupt respons...

Page 12: ...e rising edge of the strobe generates an interrupt if it has been enabled and causes the Ready line to go inactive This very simple handshake is similar to that used in many peripheral devices Selecti...

Page 13: ...interrupt is pending when the enable flag is set it will then be enabled onto the CPU interrupt request line Bits D6 D5 and D4 are used only with Mode 3 operation They are disregarded for all other m...

Page 14: ...4 3a...

Page 15: ...a duration of one clock period will be generated with no other logic required The positive edge of the strobe pulse auto matically generates an INT request if the interrupt enable flip flop has been...

Page 16: ...a onto the bus The PIG uses the B STB low level to latch this data The PIG has been designed with a zero hold time requirement for the data when latching in this mode so that this simple gating struct...

Page 17: ...rated This gives time for the Int Enable signals to ripple through up to four PIO circuits The PIO with lEI high and lEO low during INTA will place the 8 bit interrupt vector of the appropriate port o...

Page 18: ...LEDGED UNDER SERVICE SERVICE SUSPENDED 1 lEI lEO HI lEI lEO LO lEI lEO LO lEI lEO LO 3 PORT IB INTERRUPTS SUSPENDS SERVICING OF PORT 2A SERVICE COMPLETE SERVICE RESUMED 1 lEI lEO HI lEI lEO HI lEI lEO...

Page 19: ...ested an interrupt If more than four PIO devices must be accommodated a look ahead structure may be used as shown in figure 7 0 1 With this technique more than thirty PIO s may be chained together usi...

Page 20: ...for details on the operation of the interrupt V7 V6 V5 V4 V3 V2 VI Interrupts are then enabled by the rising edge of the first after the interrupt mode word is set unless that Ml defines an interrupt...

Page 21: ...3881 B A C D CE PORTA BUS SPEC TEST TURN ON PWR _ PWR FAIL ALM HALT TEMP ALM I HTRS ON PRESS SYS PRESS ALM INDUSTRIAL PROCESSING SYSTEM FIGURE 7 0 3 CONTROL MODE APPLICATION The FIG may be used as fol...

Page 22: ...D3 D2 Dl DO 1 1 1 1 then an interrupt request would also occur if bit A7 Special Test of the output register was set Assume that the following port assignments are to be used EOjj Port A Data Eljj Po...

Page 23: ...bit to Input I O Sets bit to Output SET INTERRUPT CONTROL Int AND ffigh Mask 1 1 1 Enable OR Low Follows Used in Mode 3 only If the maslc follows bit is high the next control word written to the port...

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Page 25: ...liability 9 2 D C CHARACTERISTICS TA 0 C to 70 C Vcc 5 V 5 unless otherwise specified Symbol Parameter Min Max Unit Test Condition ViLC Clock Input Low Voltage 0 3 0 6 V Clock Input High Voltage Vcc V...

Page 26: ...ing Edge of STROBE Delay to Floating Port Data Bus From Rising Edge of STROBE Port Data Stable From Rising Edge of lORQ During Write Cycle inn 120 360 200 nsec nsec nsec nsec nsec Mode 1 Mooe i Mode 2...

Page 27: ...PRELIMINARY 10 0 TIMING CHART Timing measurements are made at the following voltages unless otherwise specified 1 0 CLOCK 4 2 V 8 V OUTPUT 2 0 V 8 V INPUT 2 0 V 8 V FLOAT AV i0 5V HR Dl 25...

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