SST-DN4-PCU
Hardware Reference Guide
32
Hardware
Register
Details
©2009 Molex Inc.Automation & Electrical Products, Integrated Products Division
Document Edition: 1.0, Document #: 715-0101, Template Edition: 1.1, Template #: QMS-06-045
Use, duplication or disclosure of this document or any of the information contained herein is subject to the restrictions on page ii of this document.
3.4.2 Control Register
This register is a group of control and status bits.
Table 7: Control Register Settings
Bit
7
6
5
4
3
2
1
0
Name
CardRun MemEn IntEn WdTout
0
HostIrq0
0
CardIrq0
Read/Write
R/W
R/W
R/W R R R/W R R/W
Reset
0 0 0 0 0 0 0 0
The channel has two interrupt flags. Setting CardIrq0 generates an interrupt to the card with the
relevant flag set. When HostIrq0 is '1' and IntEn is '1', the card drives the IRQ pin (as set by
IrqLevel) high.
Table 8: Control Register Bit Descriptions
Bit Name
Description
CardRun
This bit controls and indicates whether or not the channel’s processor is running.
It also affects the Health LED.
•
When this bit is 0, the processor is halted, and the LED is RED
•
When this bit is 1, the processor is running normally, and the LED is under channel
processor control
•
When this bit is 1, and watchdog has timed out, processor is halted, and the LED is
RED
•
This bit must remain low for at least 50
μ
s to guarantee proper reset.
MemEn
This bit indicates and controls whether or not the channel’s shared memory will respond to
host memory accesses. This may be used to multiplex several SST-DN4-PCU cards or
channels at the same base address by enabling the memory on one channel at a time.
MemEn high (‘1’) enables shared memory decoding of addresses in this board’s range.
IntEn
•
Writing 1 enables interrupts
•
Writing 0 disables interrupts (the HostIrq flags still function as described)
WdTout
WdTout high (‘1’) indicates that a watchdog timeout has occurred, or that the channel’s
processor has been held in RESET by some other means. To restore this bit to 0, clear
CardRun.
HostIrq0
•
This bit is used by the channel’s processor to indicate that the channel generated an
interrupt. If IntEn is set to 1, this also means that the channel generated a physical
interrupt on the PCI bus.
•
Writing 1 acknowledges the interrupt and clears it
•
Writing 0 has no effect
•
Reading 1 indicates interrupt in progress
•
Reading 0 indicates interrupt complete
CardIrq0
This bit is used by the host to send interrupts to interrupt flag 0 of the channel’s processor.
•
Writing 1 generates an interrupt
•
Writing 0 has no effect
•
Reading 1 indicates interrupt in progress
•
Reading 0 indicates interrupt complete
