94
FX
3U
/FX
3UC
Series Programmable Controllers
Programming Manual - Basic & Applied Instruction Edition
4 Devices in Detail
4.7 High Speed Counter [C]
• A 2-phase encoder generates outputs for the A phase and the B phase by the phase difference of 90
°
.
With these outputs, a high speed counter automatically executes up-counting and down-counting as
shown in the figure below.
- When the counter is operating at the 1 edge count
- When the counter is operating at the 4 edge count
• The down/up-counting operation of C251 to C255 can be monitored by checking the ON/OFF status of
M8251 to M8255.
ON status: Down-counting
OFF status: Up-counting
4.7.4
Current value update timing and comparison of current value
1. Current value update timing
A high speed counter executes up-counting or down-counting when a pulse is input to its input terminal, but
the current value is updated at the timing shown in the table below. Accordingly, hardware counters are
affected by scans because the current value is updated at the timing shown below when the current value of
high speed counters are handled as they are in basic instructions such as MOV and CMP and applied
instructions such as the contact comparison instruction.
2. Comparison of the Current value
The following two methods are available to compare and output the current value of a high speed counter.
1) Using the comparison instruction (CMP), zone comparison instruction (ZCP) or comparison contact
instruction
When the comparison result is not required in counting, comparison is executed appropriately
*1
in the
main program if HCMOV instruction is used just before comparison instruction (CMP or ZCP) or
comparison contact instruction.
*1.
When it is necessary to execute comparison at a timing that the current value of a high speed
counter changes and to change an output contact (Y) use comparison instruction for high speed
counter (HSCS, HSCR, HSZ or HSCT).
2) Using comparison instruction for high speed counter (HSCS, HSCR, HSZ or HSCT)
The comparison instructions for high speed counter (HSCS, HSCR, HSZ and HSCT) execute comparison
and output the comparison result when a target high speed counter executes counting. The number of
using these instructions is limited as shown in the table below.
When an output relay (Y) is specified for the comparison result, the comparison result is directly reflected
on the ON/OFF status of the output without regard to the output refresh by END instruction.
Mechanical operation delay (about 10 ms) cannot be avoided in a relay output type PLC. Use a transistor
output type PLC.
*1.
When HSZ or HSCT instruction is used, the maximum response frequency and total frequency of
all software counters are affected.
→
For the maximum response frequency and total frequency of software counters,
refer to Subsection 4.7.10.
Current value update timing
Hardware counter
When OUT or HCMOV instruction is executed for counter
Software counter
When counting input is given
Instruction
Limitation in number of instruction
HSCS
Can be used up to 32 times including HSCT instruction.
HSCR
HSZ
*1
HSCT
*1
Can be used only once.
A phase
B phase
+1
+1
During forward rotation
A phase
B phase
−
1
−
1
During backward rotation
A phase
B phase
+1
During forward rotation
+1 +1 +1 +1
+1 +1 +1 +1
A phase
B phase
−
1
During backward rotation
−
1
−
1
−
1
−
1
−
1
−
1
−
1
−
1
