System Control Block Diagram
E5640BLS
1-7-1
1-7-2
59
60
49
82
IC301
(FRONT END PROCESSOR)
IC601
(DVD HOST PROCESSOR)
OSCI
OSCO
23
24
(16.9344MHz)
X301
CLOCK
X601
27MHz
120
READY
48
HANG
/FERS
TREV
TFWD
TIN
TOUT
READY
/FERS
TIN
TOUT
10
SEN
46 MUTE
47 PS
64
FROM/TO
DVD SIGNAL
PROCESS
BLOCK
DIAGRAM
FROM/TO
RF SIGNAL
PROCESS
/SERVO
BLOCK
DIAGRAM
CPUDT0
NINT1
NINT2
WAIT
/RE
/WEL
CS1
RESET
NINT1
NINT2
WAIT
/RE
/WEL
CS1
RESET
CPUDT7
13
16
26
33
35
40
~
84
91
~
~
~
~
CPUADR0
CPUADR17
~
3
VFD-STB
1
VFD-DIN
2
VFD-DOUT
125
REMOTE
204
VFD-CLK
CN501
CN1001
JP1003
JP1004
9
7
6
8
19
14
15
16
17
18
REMOTE
SENSOR
RM2001
1G
11G
~
42
32
~
a/KEY-1
b/KEY-2
c/KEY-3
d/KEY-4
e
K1
K2
FP-STB
FP-DIN
FP-DOUT
FP-CLK
GRID
FIP
SEGMENT
FL2001
IC2003
DVD MAIN CBA UNIT
AV CBA
SWITCH CBA
FG CBA
RELAY
CBA
(FRONT PANEL CONTROL)
BLOCK DIAGRAMS
TREV
TIN
TOUT
TFWD
MUTE
PS
CD/DVD
CFE
CAS
STANDBY
ADDRESS BUS
DATA BUS
CD/DVD
CFE
CAS
STANDBY
71
62
63
70
SCK
72
STDIO
SEN
SCK
STDIO
20
21
22
10
11
FG
SENSOR
CN401
FP-STB
21
21
FP-DIN
22
22
FP-DOUT
23
23
FP-CLK
24
24
REMOTE
26
26
14
80
2
4
IC102 (OP AMP)
IC606
(INVERTER)
200
RESET
124
201
187
188
208
186
FG-IN
10
41
42
52
51
50
20
21
SDA
SDA
SCL
79
SCL
KEY OUT
KEY IN
+3.3V
IRQ2
FG-IN
SDA
SCL
53
22
BUSCLR
BUSCLR
f
g
h
i
TFWD
TREV
76
77
1
2
3
6
11
RESET
IC605
5
4
Q701
+3.3V
127
44
45
12
K2
1
1
KEY-2
2
2
POWER
SW2115
KEY
MATRIX
FUNCTION CBA
CN2041
CN2001
KEY-4
1
KEY-3
2
KEY-2
3
KEY-1
4
K2
5
K1
6
1
2
3
4
5
6
23
j
OC-KEY
8
OPEN
/CLOSE
SW2044
CN501
CN1001
OC-KEY
8
OC-KEY
25
25
105
Summary of Contents for DD-4030
Page 23: ...1 8 3 1 8 4 1 8 5 E5640SCD1 DVD Main 1 4 Schematic Diagram ...
Page 24: ...DVD Main 2 4 Schematic Diagram 1 8 6 1 8 7 1 8 8 E5640SCD2 ...
Page 25: ...DVD Main 3 4 Schematic Diagram 1 8 9 1 8 10 1 8 11 E5640SCD3 ...
Page 27: ...AV 2 3 Schematic Diagram 1 8 15 1 8 16 E5640SCAV2 ...
Page 31: ...Function CBA Top View Function CBA Bottom View 1 8 23 1 8 24 BE5641F01021 ...
Page 39: ...1 15 2 E5640EX X10 X5 X2 X4 S2 S2 S4 Unit S1 A22 A30 A22 A30 X1 X31 S7 Packing ...