MiTAC E8020 User Manual Download

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4.7

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Summary of Contents for E8020

Page 1: ...E8020 OCP Computing Sled User Manual Version 1 0 ...

Page 2: ... relating to fitness for a particular purpose or merchantability MiTAC retains the right to make changes to produce descriptions and or specifications at any time without notice In no event will MiTAC be held liable for any direct or indirect incidental or consequential damage loss of use loss of data or other malady resulting from errors or inaccuracies of information contained in this document T...

Page 3: ...1 About this Manual This manual is intended for experienced users and integrators with hardware knowledge of personal computers It is aimed to provide you with instructions on installing your E8020 ...

Page 4: ...t this kind of plug contact your electrician to replace your obsolete outlet Do not place anything on the power cord Place the power cord where it will not be in the way of foot traffic Follow all warnings and cautions in this manual and on the unit case Do not push objects in the ventilation slots as they may touch high voltage components and result in shock and damage to the components When repl...

Page 5: ...in which you install the system is properly ventilated and climate controlled Ensure that the voltage and frequency of your power source match the voltage and frequency inscribed on the electrical rating label of the equipment Do not install the system in or near a plenum air duct radiator or heat register Never use the product in a wet location Equipment Chassis Do not block or cover the openings...

Page 6: ...I O 32 3 3 LED Indicators 33 3 4 Block Diagram 34 4 BIOS UEFI 35 4 1 BIOS Setup Utility 35 4 2 Main 39 4 3 Advanced 40 4 4 Chipset 67 4 5 AMD CBS 69 4 6 Server Mgmt 83 4 7 Security 86 4 8 Boot 88 4 9 Save Exit 89 5 BMC 91 5 1 BMC introduction 91 5 2 BMC connectivity 91 5 3 Local Serial Console and SOL 92 5 4 Sensors 92 5 5 Commands Support 105 6 FIRMWARE UPDATE 121 6 1 BIOS Update 121 6 2 Firmware...

Page 7: ...2 APPENDIX A 124 ...

Page 8: ...8020 OCP system E8020 is a highly optimized OCP system It is based on AMD EPYC 7002 Serial Rome product family CPU architecture and 7003 Milan CPU will also be supported It supports up to 8 DIMMs E8020 motherboard is designed to work with Open Rack V2 Orv2 described in the following chapter ...

Page 9: ... C USB 3 0 Storage 6 x 2 5 SATA SSD bay Front 6 x 2 5 U 2 SSD bay Rear 4 x 2 5 hot swappable U 2 bay Front 6 x 2 5 U 2 SSD bay Rear Storage OS usage only M 2 SATA or NVMe PCIe Expansion Slots 2 HHHL PCIe Gen 4 x16 Slots 1 FHHL PCIe Gen 4 x16 Slot Mezzanine Slots OCP V2 0 NIC mezz compatible Server Management IPMI 2 0 compliant baseboard management controller BMC Web interface support Onboard Aspee...

Page 10: ...different configurations On the rear end there is a floating connector that fits into bus bar providing power to this sled There are sharp edges on the metal parts This is generic to the low cost OCP design Be sure to wear gloves when you assemble disassemble any mechanical components For example PCIe bracket PCIe cards and installing cables etc ...

Page 11: ...ing Up 2 1 System SKUs MiTAC E8020 server has two hardware configurations which is Advanced and Ultra 2 1 1 Advanced Note Support 6x 7mm thickness SSD SATA drives using PCH SATA or a HBA card 2x HHHL PCIe cards ...

Page 12: ...7 2 1 2 Ultra Note 4x U 2 drives One FHHL PCIe card ...

Page 13: ...ion describes how to install components on to the mainboard including CPUs memory modules adapter Card Drive and Add On cards 2 2 1 Removing the Chassis Cover Follow these instructions to remove chassis cover Push the top cover in the arrow direction ...

Page 14: ... Screw 2 and lastly Screw 1 Screw numbers are marked next to the screws on the Force Frame The spring loaded Force Frame will raise up to beyond the vertical position 105 degrees on its pivot hinge after the last Screw 1 is completely un threaded Hold and rotate the Force Frame until it has come to the final open position before releasing finger grasp on the Force Frame As can be seen above both t...

Page 15: ...ng loaded thus please hold on to the Rail Frame as it is dis engaged from the Socket Housing While holding the Rail Frame slowly rotate the Rail Frame to the vertical position Do not release the Rail Frame until it is in the vertical position since the spring force for the Rail Frame is optimized for the heavier CPU package The lighter External Cap currently in the Rail Frame can produce an abrupt...

Page 16: ...ame will come to a stop in the vertical position for subsequent operations Note Do not remove the PnP Cover Cap at this point of the installation procedure to prevent accidental contact damage in the subsequent steps ...

Page 17: ...e rail guides on the Rail Frame CPU Package is shipped from AMD factory with the blue Carrier Frame pre assembled Upper picture Top view showing the lid side of the Carrier Frame CPU Package assembly Lower picture Bottom view showing the land pad side of the Carrier Frame CPU Package assembly ...

Page 18: ...ackage shipping tray While gripping the handle of the Carrier Frame align the flange features on the Carrier Frame with the rail guides on the Rail Frame and slide the Carrier Frame downwards Check to ensure that the flange features on the Carrier Frame are inserted into the rail guides of the Rail Frame ...

Page 19: ...l Frame The Carrier Frame CPU Package assembly is now completely loaded onto the Rail Frame The PnP Cover Cap can now be removed Grip the two lift tabs marked REMOVE at the middle of the long sides of the PnP Cover Cap and pull vertically upwards to remove the PnP Cover Cap from the Socket Housing Be very careful not to drop the PnP Cover Cap into the exposed contact field during the removal proce...

Page 20: ...plicable for the first CPU Package insertion only The PnP Cover Cap is not replaced onto the Socket Housing after the first CPU Package removal to avoid the risk of damaging the contacts during PnP Cover Cap replacement procedure Henceforth the contacts in the Socket Housing are protected by the External Cap Grip the lift tabs at the top of the Rail Frame and rotate the Rail Frame with locked Carr...

Page 21: ...lignment features on the Carrier Frame and Socket Housing ensures that the CPU Package is properly seated in the Socket Housing With the CPU Package properly seated in the Socket Housing the Rail Frame will latch to the Socket Housing and remain in the horizontal position without being held down anymore The socket is now ready for actuation ...

Page 22: ... over the CPU Package seating in the Socket Housing Rotate the Force Frame until it is in the horizontal position At this horizontal position the three captive screws with Torx T20 head in the Force Frame will align with the PEM nuts on the Stiffener Frame ...

Page 23: ...f cm 14 0 lbf in and fitted with a Torx T20 screw head bit Note the CLOSE 1 2 3 screw threading sequence printed on the top of the Force Frame Engage and tighten Screw 2 Note The three captive screws on the Force Frame can be tightened in its entirety in a single threading sequence there is no need to alternate between screws for multiple partial threading and tightening sequence for these three s...

Page 24: ...ATED with electrical connectivity between the PCB and the CPU Package provided by the socket contacts Caution The screw tightening sequence of 1 2 3 must be executed in proper sequence to avoid causing catastrophic damage to the socket and or CPU Package ...

Page 25: ...e installed on top of the CPU Package lid by securing the four captive screws on the heatsink base to the four PEM nuts on the Stiffener Frame shown in red circles above The screw and PEM nuts are located asymmetrically so that the heatsink can be installed in the correct orientation only The heatsink uses the same Torx T20 head screws as the Socket Actuation Mechanism ...

Page 26: ... within red circles above on the Heatsink base to the PEM nuts on the Stiffener Frame in a clockwise direction Use the same the torque screw driver setting at 16 1 kgf cm 14 0 lbf in and a Torx T20 screw head bit to install the heatsink onto the Socket Actuation Mechanism ...

Page 27: ...nstructions to install the memory modules onto the motherboard A Press the memory slot latch outward B Align the memory module with the slot When insert properly the memory slot latches automatically onto the indentations at two ends of the module ...

Page 28: ...g the Drive 6SSD configuration for example E8020 Advanced server supports 6 2 5 SSD Following the instructions to install the SSD A Insert the Drive into the Drive bracket in the direction of arrow until you hear a click ...

Page 29: ...24 2 2 5 Release the Drive A Pull the locking Drive lever open in the direction of arrow B Take out Drive ...

Page 30: ...25 2 2 6 Install M 2 device First to remove the rear Drive Cage Insert the M 2 device into the connector and push down ...

Page 31: ...e slots available on PCIe riser board You can install the add on cards into the expansion slot of riser which is integrated with the bracket The following instructions are for add on card installation A The Drive cage aliment to the sled and install it ...

Page 32: ...27 B Push the Right Left handle bar to lock the Drive Cage ...

Page 33: ...28 C Insert the Riser Card ...

Page 34: ...29 D Fasten the latch to lock the riser card E Open the retainer as shown ...

Page 35: ...30 F Insert the PCI card into the slot of riser board as shown G Close the retainer to fully secure the PCIe card ...

Page 36: ...31 3 Mainboard Information 3 1 Board Introduction Here are different views of the main board ...

Page 37: ...10 2 Reset button 12 Connector for VGA 3 SATA port for SATA drive 13 Type C USB 4 Power for SATA drive 14 Type A USB 5 Two miniSASHD ports for external SATA drives 15 Connector for debug board optional 6 Power for external SATA drives 7 Fan conntector 8 Power cable 9 M 2 slot 10 Battery ...

Page 38: ...ndicators LED LED Color Behavior LED Location 1 Power LED Blue Power on U31 2 Drive LED Green Twinkling as M 2 active U45 3 BMC Heartbeat Green BMC FW initialize D18 4 CPLD Heartbeat Orange CPLD FW initialize LED4 ...

Page 39: ...34 3 4 Block Diagram ...

Page 40: ...links lead to pages containing a specific category s configuration Console Redirection BIOS Setup is functional via Console Redirection over various terminal emulation standards When Console Redirection is enabled the POST display out is in Text Mode due to Redirection data transfer in a serial port data terminal emulation mode Entering BIOS Setup To enter the BIOS Setup using a keyboard or emulat...

Page 41: ...o select a subfield for multi valued features like time and date If a pick list is displayed the Enter key selects the currently highlighted item undoes the pick list and returns the select item Change value The plus minus key on the keypad is used to change the value of the current item to the next previous value This key scrolls through the values in the associated pick list without displaying t...

Page 42: ...ts Yes No If Yes is highlighted and Enter is pressed all Setup fields are set to their default values If No is highlighted and Enter is pressed or if the ESC key is pressed the user is returned to where they were before F9 was pressed without affecting any existing field values F10 Save and Exit Pressing the F10 key causes the following message to display Save configuration and exit Yes No If Yes ...

Page 43: ...and the Enter key is pressed the setup is exited and the BIOS reset the system BIOS Setup Utility Screens Setup Menu Screen contains the entire BIOS Setup collection and organizes them into many categories Each category has a hierarchy with a top level screen from which lower level screens may be selected The default setting of option is marked by blue color and star sign NOTE The following pages ...

Page 44: ...anguage English Choose the system default language Dynamic System Date Set the Date Use Tab to switch between Date elements Default Ranges Year 2005 2099 Months 1 12 Days dependent on month Dynamic System Time Set the Time Use Tab to switch between Time elements ...

Page 45: ...Configuration CSM configuration Enable Disable Option ROM execution settings etc Submenu USB Configuration USB Configuration Parameters Submenu NVMe Configuration NVMe Devices Information Submenu SATA Configuration SATA Devices Information Submenu Trusted Computing Trusted Computing Settings Submenu AST2500 Super IO Configuration System Super IO Chip Parameters Submenu Driver Health Provides Healt...

Page 46: ... I210 Gigabit Network Connection A0 42 3F 3A E5 E1 Configure Gigabit Ethernet device parameters 4 3 1 CPU Configuration Type Option Name Options Help Multipart SVM Mode Disabled Enabled Enable disable CPU Virtualization Multipart SMEE Disabled Enabled Control secure memory encryption enable Submenu CPU 0 Information View Information related to CPU 0 ...

Page 47: ...42 CPU 0 Information ...

Page 48: ...43 4 3 2 ACPI Settings No Option Name Options Help Multipart Enable ACPI Auto Configuration Disabled Enabled Enables or Disables BIOS ACPI Auto Configuration ...

Page 49: ...n Name Options Help Multipart Authentication mode Basic Authentication Session Authentication Select authentication mode Numeric IP Address 0 0 0 0 Enter IP address Numeric IP Mask address 0 0 0 0 Enter IP Mask address Numeric IP Port 443 Enter IP port ...

Page 50: ...45 4 3 4 Serial Port Console Redirection ...

Page 51: ...nable or Disable Submenu Console Redirection Settings The settings specify how the host computer and the remote computer which the user is using will exchange data Both computers should have the same or compatible settings Submenu Legacy Console Redirection Settings Legacy Console Redirection Settings Multipart Console Redirection Disabled Enabled Console Redirection Enable or Disable Submenu Cons...

Page 52: ...elects serial port transmission speed The speed must be matched on the other side Long or noisy lines may require lower speeds Multipart Data Bits 7 8 Data Bits Multipart Parity None Even Odd Mark Space A parity bit can be sent with the data bits to detect some transmission errors Even parity bit is 0 if the num of 1 s in the data bits is even Odd parity bit is 0 if num of 1 s in the data bits is ...

Page 53: ...nt to stop the data flow Once the buffers are empty a start signal can be sent to re start the flow Hardware flow control uses two wires to send start stop signals Multipart VT UTF8 Combo Key Support Disabled Enabled Enable VT UTF8 Combination Key Support for ANSI VT100 terminals Multipart Recorder Mode Disabled Enabled With this mode enabled only text will be sent This is to capture Terminal data...

Page 54: ...49 Console Redirection Settings COM1 ...

Page 55: ...rity bit is always 1 Space Parity bit is always 0 Mark and Space Parity do not allow for error detection They can be used as an additional data bit Multipart Stop Bits 1 2 Stop bits indicate the end of a serial data packet A start bit indicates the beginning The standard setting is 1 stop bit Communication with slow devices may require more than 1 stop bit Multipart Flow Control None Hardware RTS ...

Page 56: ...51 Multipart Resolution 100x31 Disabled Enabled Enables or disables extended terminal resolution Multipart Putty KeyPad VT100 LINUX XTERMR6 SCO ESCN VT400 Select FunctionKey and KeyPad on Putty ...

Page 57: ...tipart Resolution 80x24 80x25 On Legacy OS the Number of Rows and Columns supported redirection Multipart Redirect After POST Always Enable BootLoader When Bootloader is selected then Legacy Console Redirection is disabled before booting to legacy OS When Always Enable is selected then Legacy Console Redirection is enabled for legacy OS Default setting for this option is set to Always Enable ...

Page 58: ...sole Redirection Settings page for more Help with Terminal Type Emulation Multipart Bits per second 9600 19200 57600 115200 Selects serial port transmission speed The speed must be matched on the other side Long or noisy lines may require lower speeds Multipart Flow Control None Hardware RTS CTS Software Xon Xoff Flow control can prevent data loss from buffer overflow When sending data if the rece...

Page 59: ...s 64bit capable Devices to be Decoded in Above 4G Address Space Only if System Supports 64 bit PCI Decoding Multipart SR IOV Support Disabled Enabled If system has SR IOV capable PCIe Devices this option Enables or Disables Single Root IO Virtualization Support Submenu PCI Express Settings Change PCI Express Devices Settings ...

Page 60: ... Settings Tyep Option Name Options Help Multipart Maximum Payload Auto 128 Bytes 256 Bytes 512 Bytes 1024 Bytes 2048 Bytes 4096 Bytes Set Maximum Payload of PCI Express Device or allow System BIOS to select the value ...

Page 61: ...p Current Set display mode for Option ROM Multipart Network UEFI Legacy Controls the execution of UEFI and Legacy Network OpROM Multipart Storage UEFI Legacy Controls the execution of UEFI and Legacy Storage OpROM Multipart Video UEFI Legacy Controls the execution of UEFI and Legacy Video OpROM Multipart Other PCI devices UEFI Legacy Determines OpROM execution policy for devices other than Network...

Page 62: ...57 4 3 7 USB Configuration ...

Page 63: ...0 64 Emulation Disabled Enabled Enables I O port 60h 64h emulation support This should be enabled for the complete USB keyboard legacy support for non USB aware OSes Multipart USB transfer time out 1 sec 5 sec 10 sec 20 sec The time out value for Control Bulk and Interrupt transfers Multipart Device reset time out 10 sec 20 sec 30 sec 40 sec USB mass storage device Start Unit command time out Mult...

Page 64: ...lp Multip art Security Device Support Disable d Enabled Enables or Disables BIOS support for security device O S will not show Security Device TCG EFI protocol and INT1A interface will not be available Multip art Disable Block Sid Disable d Enabled Override to allow SID authentication in TCG Storage device ...

Page 65: ...AST2500 Super IO Configuration No Option Name Options Help Submenu Serial Port 1 Configuration Set Parameters of Serial Port 1 COMA Submenu Serial Port 2 Configuration Set Parameters of Serial Port 2 COMB ...

Page 66: ...Port Disabled Enabled Enable or Disable Serial Port COM Multipart Change Settings Auto IO 3F8h IRQ 4 IO 3F8h IRQ 3 4 5 6 7 9 10 11 12 IO 2F8h IRQ 3 4 5 6 7 9 10 11 12 IO 3E8h IRQ 3 4 5 6 7 9 10 11 12 IO 2E8h IRQ 3 4 5 6 7 9 10 11 12 Select an optimal settings for Super IO Device ...

Page 67: ...Port Disabled Enabled Enable or Disable Serial Port COM Multipart Change Settings Auto IO 2F8h IRQ 3 IO 3F8h IRQ 3 4 5 6 7 9 10 11 12 IO 2F8h IRQ 3 4 5 6 7 9 10 11 12 IO 3E8h IRQ 3 4 5 6 7 9 10 11 12 IO 2E8h IRQ 3 4 5 6 7 9 10 11 12 Select an optimal settings for Super IO Device ...

Page 68: ...art Ipv6 PXE Support Disabled Enabled Enable Disable IPv6 PXE boot support If disabled IPv6 PXE boot support will not be available Multipart Ipv6 HTTP Support Disabled Enabled Enable Disable IPv6 HTTP boot support If disabled IPv6 HTTP boot support will not be available Multipart IPSEC Certificate Disabled Enabled Support to Enable Disable IPSEC certificate for Ikev Numeric PXE boot wait time 0 Wa...

Page 69: ...64 4 3 12 iSCSI Configuration Type Option Name Options Help Executing iSCSI Initiator Name The worldwide unique name of iSCSI Initiator Only IQN format is accepted Range is from 4 to 223 ...

Page 70: ...3 13 Intel R I210 Gigabit Network Connection Type Option Name Options Help Submenu NIC Configuration Click to configure the network device port Numeric Blink LEDs 0 Blink LEDs for a duration up to 15 seconds ...

Page 71: ...bps Full 100 Mbps Half 100 Mbps Full Specifies the port speed used for the selected boot protocol Multipart Wake On LAN Disabled Enabled Enables power on of the system via LAN Note that configuring Wake on LAN in the operating system does not change the value of this setting but does override the behavior ...

Page 72: ...7 4 4 Chipset Type Option Name Options Help Submenu North Bridge North Bridge Parameters 4 4 1 North Bridge Type Option Name Options Help Submenu Socket 0 Information View Information related to Socket 0 ...

Page 73: ...68 Socket 0 Information View Information related to Socket 0 ...

Page 74: ...S Type Option Name Options Help Submenu CPU Common Options CPU Common Options Submenu DF Common Options DF Common Options Submenu UMC Common Options UMC Common Options Submenu NBIO Common Options NBIO Common Options ...

Page 75: ...Platform First Error Handling Enabled Disabled Auto Enable disable PFEH cloak individual banks and mask deferred error interrupts from each bank Multip art Core Performance Boost Disabled Auto Disable CPB Multip art Global C state Control Disabled Enabled Auto Controls IO based C state generation and DF C states Multip art SEV ES ASID Space Limit Control Auto Manual No help string ...

Page 76: ...ctions to take effect Multipart Core control Auto TWO 1 1 FOUR 2 2 SIX 3 3 Sets the number of cores to be used Once this option has been used to remove any cores a POWER CYCLE is required in order for future selections to take effect Multipart SMT Control Auto Disabled Can be used to disable symmetric multithreading To re enable SMT a POWER CYCLE is needed after selecting the Auto option WARNING S...

Page 77: ...ption Name Options Help Multipart L1 Stream HW Prefetcher Disable Enabled Auto Option to Enable Disable L1 Stream HW Prefetcher Multipart L2 Stream HW Prefetcher Disable Enabled Auto Option to Enable Disable L2 Stream HW Prefetcher ...

Page 78: ...73 4 5 2 DF Common Options Type Option Name Options Help Submenu Scrubber Scrubber Submenu Memory Addressing Memory Addressing ...

Page 79: ...ours 16 hours 24 hours 48 hours Auto Provide a value that is the number of hours to scrub memory Multipart Poison scrubber control Disabled Enabled Auto Control DF RedirScrubCtrl RedirScrubMode 1 Multipart Redirect scrubber control Disabled Enabled Auto Control DF RedirScrubCtrl RedirScrubMode 0 ...

Page 80: ...gether Multip art Memory interleaving Disabled Auto Allows for disabling memory interleaving Note that NUMA nodes per socket will be honored regardless of this setting Multip art Memory interleaving size 256 Bytes 512 Bytes 1 KB 2 KB Auto Controls the memory interleaving size The valid values are AUTO 256 bytes 512 bytes 1 Kbytes or 2Kbytes This determines the starting address of the interleave bi...

Page 81: ...76 4 5 3 UMC Common Options Type Option Name Options Help Submenu DDR4 Common Options DDR4 Common Options Submenu DRAM Memory Mapping DRAM Memory Mapping ...

Page 82: ...77 DDR4 Common Options Type Option Name Options Help Submenu DRAM Timing Configuration DRAM Timing Configuration Submenu Common RAS Common RAS Submenu Security Security ...

Page 83: ...Memory Clock Speed Auto 2666Mhz 2933MHz 3200MHz Specifies the memory clock frequency Common RAS Type Option Name Options Help Multipart Data Poisoning Disabled Enabled Auto Enable disable data poisoning UMC_CH EccCtrl UcFatalEn UMC_CH EccCtrl WrEccEn Should be enabled disabled together Submenu ECC Configuration ECC Configuration ...

Page 84: ...DRAM ECC Symbol Size x4 x8 x16 UMC_CH EccCtrl EccSymbolSize16 EccSymbolSize Multipart DRAM ECC Enable Disabled Enabled Auto Use this option to enable disable DRAM ECC Auto will set ECC to enable Security Type Option Name Options Help Multipart Data Scramble Enabled Disabled Auto Data scrambling DataScrambleEn ...

Page 85: ...locks across the DRAM chip selects for node 0 Multipart BankGroupSwap Enabled Disabled Auto BankGroupSwapAlt default Enabled in BIOS which has priority than BankGroupSwap BIOS equation If BankGroupSwapAlt Enabled Then BankGroupSwap Disabled Endif Please set BankGroupSwapAlt to Disabled while set BankGroupSwap to Enabled ...

Page 86: ...MMU Disabled Enabled Auto Enable Disable IOMMU Multipart ACS Enable Enabled Disabled Auto AER must be enabled for ACS enable to work Multipart PCIe ARI Support Disabled Enabled Auto Enables Alternative Routing ID Interpretation Submenu SMU Common Options SMU Common Options ...

Page 87: ...User can set customized Determinism Multipart cTDP Control Manual Auto Auto Use the fused TDP Manual User can set customized TDP Multipart Package Power Limit Control Manual Auto Auto Use the fused PPT Manual User can set customized PPT PPT will be used as the ASIC power limit Numeric Package Power Limit 0 Package Power Limit PPT W ...

Page 88: ...5 minutes Enter value Between 3 to 15 min for FRB 2 Timer Expiration value Multipart FRB 2 Timer Policy Do Nothing Reset Power Down Power Cycle Configure how the system should respond if the FRB 2 Timer expires Not available if FRB 2 Timer is disabled Multipart OS Watchdog Timer Enabled Disabled If enabled starts a BIOS timer which can only be shut off by Management Software after the OS loads Hel...

Page 89: ...Wtd Timer Policy Do Nothing Reset Power Down Configure how the system should respond if the OS Boot Watchdog Timer expires Not available if OS Boot Watchdog Timer is disabled Multipart Power Restore Policy always off last state always on Select always on always off last state for ACPI state after a G3 Multipart When SEL is Full Do Nothing Erase Immediately SEL Circular Choose options for reactions...

Page 90: ...namically by BIOS or BMC Unspecified option will not modify any BMC network parameters during BIOS phase Multipart IPv6 Support Disabled Enabled Enable or Disable LAN1 IPv6 Support Multipart Configuration Address source Unspecified Static DynamicBmcDhcp Select to configure LAN channel parameters statically or dynamically by BIOS or BMC Unspecified option will not modify any BMC network parameters ...

Page 91: ...86 4 7 Security Type Option Name Options Help Password Administrator Password Set Administrator Password Password User Password Set User Password Submenu Secure Boot Secure Boot configuration ...

Page 92: ... Custom Secure Boot mode options Standard or Custom In Custom mode Secure Boot Policy variables can be configured by a physically present user without full authentication Execu ting Restore Factory Keys Yes No Force System to User Mode Install factory default Secure Boot key databases Execu ting Reset To Setup Mode Yes No Delete all Secure Boot key databases from NVRAM Subm enu Key Management Enab...

Page 93: ...he keyboard NumLock state Multipart Quiet Boot Disabled Enabled Enables or disables Quiet Boot option Multipart Endless Boot Support Disabled Enabled Enables or disables Endless Boot Support option Dynamic Multipart Boot Option 1 Boot option name 1 Boot option name 2 Disabled Sets the system boot order Dynamic Multipart Boot Option 2 Boot option name 2 Boot option name 1 Disabled Sets the system b...

Page 94: ...89 4 9 Save Exit ...

Page 95: ...p without saving any changes Executing Save Changes Yes No Save Changes done so far to any of the setup options Executing Discard Changes Yes No Discard Changes done so far to any of the setup options Executing Restore Defaults Yes No Restore Load Default values for all the setup options Executing Save as User Defaults Yes No Save the changes done so far as User Defaults Executing Restore User Def...

Page 96: ...el I210 AT Intel I210 AT has 10 100 1000 MDI interface to RJ45 Option 3 Dedicated NIC uses RMII NCSI interfaces to pass management traffic on data network on Intel I210 AT Intel I210 AT connection to host is disabled If Option 2 exists BMC uses RJ45 on board Intel I210 as default E8020 BMC management network firmware and utility supports all features defined in this specification in both IPv4 and ...

Page 97: ...Before the system has first screen POST codes are dumped to and displayed in SOL console in sequence For example display as 00 01 02 E0 etc BMC also stores up to 256 POST codes for debugging purpose After the system has first screen in SOL console the last POST code received on port 80 is displayed in the lower right corner of SOL console screen 5 4 Sensors The Table below shows the IPMI sensors m...

Page 98: ...PU VR PIN 11h 0BH 01H 01H 20H 03H 00H UC HSC Input Power 29H 0BH 01H 01H 20H 07H 00H UC HSC Output Curr 28H 03H 01H 01H 20H 07H 00H UC HSC Input Volt 2AH 02H 01H 01H 20H 07H 00H LC UC CPU Pkg Power 2CH 0BH 01H 01H 20H 07H 00H NA CPU VR POUT 22H 0BH 01H 01H 20H 14H 00H UC CPU VR Curr 23H 03H 01H 01H 20H 14H 00H UC CPU VR Volt 24H 02H 01H 01H 20H 14H 00H LC UC DIMM VR0 POUT 32H 0BH 01H 01H 20H 14H 0...

Page 99: ... 01H 01H 20H 07H 00H LC UC Front U2SSD Temp B9H 01H 01H 01H 20H 04H 00H LC UC Rear U2SSD Temp BAH 01H 01H 01H 20H 04H 00H LC UC PCIe card Temp 64H 01H 01H 01H 20H 07H 00H LC UC Discrete Sensors System Status 10H 0BH 6FH 02H 20H 07H 00H 0 1b CPU0 socket occupied 2 1b CPU0 Thermal trip 7 1b System throttle SEL Status 5FH 0BH 6FH 02H 20H D0H 00H 02h SEL Clear 08h SEL Rollover DCMI Watchdog 60H 23H 6F...

Page 100: ...s Low 2EH 0BH 6FH 02H 20H 14H 00H 0 1b NONEABOVE_STATUS 1 1b CML_FAULT 2 1b TEMP_FAULT 3 1b VIN UV FAULT 4 1b IOUT OC FAULT 5 1b VOUT OV FAULT 6 1b HOTSWAP_OFF 7 1b BUSY HSC Sts High 2FH 0BH 6FH 02H 20H 14H 01H 0 1b Unknown 1 1b Other 2 1b Fans 3 1b Power Good 4 1b MFR Specific 5 1b Input 6 1b Iout Pout 7 1b Vout CPU Error 91H 0BH 6FH 02H 20H 03H 00H 3 Thermal Trip Front SSD Slot0 66H 0Dh 6FH 02H ...

Page 101: ... 0 1b Drive Presence 1 1b Drive Fault 2 1b Predictive Failure 3 1b Hot Spare 4 1b Parity Check In Progress 5 1b In Critical Array 6 1b In Failed Array 7 1b Rebuild In Progress Front SSD Slot3 69H 0Dh 6FH 02H 20H 04H 04H 0 1b Drive Presence 1 1b Drive Fault 2 1b Predictive Failure 3 1b Hot Spare 4 1b Parity Check In Progress 5 1b In Critical Array 6 1b In Failed Array 7 1b Rebuild In Progress Rear ...

Page 102: ...0 1b Drive Presence 1 1b Drive Fault 2 1b Predictive Failure 3 1b Hot Spare 4 1b Parity Check In Progress 5 1b In Critical Array 6 1b In Failed Array 7 1b Rebuild In Progress Rear SSD Slot3 6DH 0Dh 6FH 02H 20H 04H 08H 0 1b Drive Presence 1 1b Drive Fault 2 1b Predictive Failure 3 1b Hot Spare 4 1b Parity Check In Progress 5 1b In Critical Array 6 1b In Failed Array 7 1b Rebuild In Progress Rear SS...

Page 103: ... Hot Spare 4 1b Parity Check In Progress 5 1b In Critical Array 6 1b In Failed Array 7 1b Rebuild In Progress Note 1 Refer to IPMI 2 0 Table 43 1 byte 8 2 Refer to IPMI 2 0 Table 43 1 byte 13 3 Refer to IPMI 2 0 Table 43 1 byte 14 4 Refer to IPMI 2 0 Table 43 1 byte 9 5 Refer to IPMI 2 0 Table 43 1 byte 9 6 Refer to IPMI 2 0 Table 43 1 byte 15 20 7 Enabled condition 0 Always Enable 1 Power on 2 BI...

Page 104: ... Event Data2 Machine Check bank Number Any one of 0 to 21 Event Data3 7 5 CPU Number 4 0 Core Number PCIe Error 0x41 0x0001 Event Data1 7 6 10b 5 4 10b 3 0 04h PCI PERR 05h PCI SERR 07h correctable 08h uncorrectable 0Ah Bus Fatal Event Data2 7 3 Device Number 2 0 Func Number Event Data3 7 0 Bus No Other IIO Err 0x43 0x0001 Event Data1 7 6 10b 5 4 10b 3 0 Offset 0x00 Other IIO Event Data2 7 0 Error...

Page 105: ...valid 01b DIMM info invalid 10b All info invalid 1 0 Logical Rank Event Data3 7 5 CPU Number 4 2 Channel Number 1 0 DIMM Number Software NMI 0x90 0x0001 Event Data1 7 6 00b Unspecified byte2 5 4 00b Unspecified byte3 3 0 03h Software NMI Event Data2 FFh Not Used Event Data3 FFh Not Used Button 0xAA 0x0020 Event Data1 7 4 0h 3 0 0h Power button pressed 2h Reset button pressed Event Data2 FFh Not Us...

Page 106: ... ping gateway after disconnection state Event Data2 FFh Not Used Event Data3 FFh Not Used System Event 0xE9 0x0020 Event Data1 7 0 E5h Timestamp Clock synch 7 0 C4h PEF Action Event Data2 if ED1 E5h 0x00 event is first of pair 0x80 event is second of pair if ED1 C4h 0x1 PEF Action Event Data3 if ED1 E5h Cause of time changed 00h NTP 01h Host RTC 02h Set SEL time command 03h Set SEL time UTC offset...

Page 107: ... provided later when it is available Table 5 3 IPMI 2 0 Thresholds Specification Term Full Name Description LNR Lower non recoverable Anything below causes power down LC Lower critical Below this point the shelf will take action LNC Lower non critical Above this point is the normal operating point UNC Upper non critical below this point is the normal operating point UC Upper critical above this po...

Page 108: ... D7H 0x80 2 701 0xab 3 608 y 0 0211x Front U2SSD Temp B9H 0x5 5 0 10 65 0x46 70 y x Rear U2SSD Temp BAH 0x5 5 0 10 65 0x46 70 y x PCIe card Temp 64H 0x5 5 10 90 0x69 105 y x Sensor Description Sensor No LNR LC raw data LC real value LNC UNC UC raw data UC real value UNR Formula 1 Outlet Temp 01H 0x5 5 10 70 0x4b 75 y x Inlet Temp 07H 0x5 5 10 40 0x2D 45 y x CPU Temp 05H 0x5 5 10 90 0x64 100 y x CP...

Page 109: ...104 Note 1 Refer to IPMI 2 0 Section 36 3 where y Converted reading x Raw reading Table 10 below provides the converted reading for maintenance 2 2 s complement for negative value ...

Page 110: ...many optional commands The following is a list of commands that currently support to the Capri BMC firmware IPMI Global Commands IPM Global Commands Get Device ID Cold Reset Warm Reset Get Self Test Results Set ACPI Power State Get ACPI Power State Get Device GUID Get NetFn Support Get Command Support Get Command Sub function Support Get Configurable Get Configurable Command Sub functions BMC Watc...

Page 111: ...GUID Get Channel Authentication Capabilities Get Session Challenge Activate Session Set Session Privilege Level Close Session Get Session Info Get AuthCode Set Channel Access Get Channel Access Get Channel Info Set Channel Security Keys Set User Access Get User Access Set User Name Get User Name Set User Password Master Write Read Get Channel Cipher Suites Get System Interface Capabilities Set Sys...

Page 112: ...nnel Payload Version Get Channel OEM Payload Info Suspend Resume Payload Encryption Chassis Device Commands Chassis Device Commands Get Chassis Capabilities Get Chassis Status Chassis Control Chassis Identify Set Chassis Capabilities Set Power Restore Policy disable by default Get System Restart Cause Set System Boot Options Get System Boot Options Get POH Counter Event Commands Event Commands Set...

Page 113: ...ledge Sensor Device Commands Sensor Device Commands Get Device SDR Info Get Sensor Reading Factors Set Sensor Hysteresis Get Sensor Hysteresis Set Sensor Threshold Get Sensor Threshold Set Sensor Event Enable Get Sensor Event Enable Re arm Sensor Events Get Sensor Event Status Get Sensor Reading Set Sensor Reading And Event Status Set Sensor Type FRU Inventory Area Info FRU Device Commands Get FRU...

Page 114: ...me Enter SDR Repository Update Mode Exit SDR Repository Update Mode Run Initialization Agent SEL Device Commands SEL Device Commands Get SEL Info Get SEL Allocation Info Reserve SEL Get SEL Entry Add SEL Entry Partial Add SEL Entry Clear SEL Get SEL Time Set SEL Time Get SEL Time UTC Offset Set SEL Time UTC Offset IPMI LAN Commands IPMI LAN Commands Set LAN Configuration Parameters Get LAN Configu...

Page 115: ... Table 5 5 OEM Commands Synopsis Command Set Sub command NetFn CMD Code FSC Command Set Restore FSC Command 30h 72h Get PWM value Command 30h 69h Set PWM value Command 30h 70h Auto BIOS Recovering command Set Set Dual BIOS Mux Command 30h 43h Set Dual BIOS Recovery Command 30h 44h Get Dual BIOS Status Command 30h 45h Set Dual BIOS Version Obtain Command 30h 54h Get Dual BIOS Version Command 30h 50...

Page 116: ...eplay SOL Buffer Command 30h 48h Set PPIN Command 30h 77h Get PPIN Command 30h 78h Set Preserve Configuration Command 32h 83h Get Preserve Configuration Command 32h 84h Set First Time BIOS Boot Flag Command 30h 40h Set PHY Reset Status Command 30h 30h Get PHY Reset Status Command 30h 31h Set GPIO Command 30h E0h Get GPIO Command 30h E1h Getting Multiple IPv6 IP Addresses command 32h 99h Get PIN 30...

Page 117: ... Information Product ID Manufacturer ID Remove all the special settings such as different priority but SEL will not remove Note The BMC will reset itself after restore to default Get 80 Port Record Command Net Function 30h OEM Code Command Request Response Data Description 49h Get 80 Port Record Request N A Response Byte 1 Completion code Byte 2 N POST code Replay the last port 80 POST codes up to...

Page 118: ... card is priority 2 Get Network Sequence Command Net Function 30h OEM Code Command Request Response Data Description B1h Get Network Sequence Request N A Response Byte 1 Completion code Byte 2 00h LOM I210 is priority 1 Mezzanine card is priority 2 01h Mezzanine card is priority 1 LOM I210 is priority 2 Read setting of OOB interface priority The Network sequence priority default is LOM I210 Byte 2...

Page 119: ...to 60 seconds Get Board ID Command Net Function 3Ch OEM Code Command Request Response Data Description 89h Get Board ID Request N A Response Byte 1 Completion code Byte 2 09h SKU1 0ah SKU2 0bh SKU3 0ch SKU4 Read Board SKU ID pin status Get FAB Revision ID Command Net Function 3Ch OEM Code Command Request Response Data Description 8Ah Get FAB Revision ID Request N A Response Byte 1 Completion code ...

Page 120: ...tify Interval in seconds 1 based Timing accuracy 0 20 This field is optional If this byte is not provided the default timeout shall be 15 seconds 0 20 Note that this byte can be overridden by optional byte 2 00h Turn off Identify Byte 2 Force Identify On This optional field enables software to command the Identify to be On indefinitely The BMC implementation should return an error completion code ...

Page 121: ...unctions These functions will be controlled externally through the IPMI chassis commands that described in the IPMIv2 0 specification Including Get chassis capabilities Get chassis status and chassis control Power down Power up Power cycle Hard Reset Power Button Logging BMC has the ability to generate unique events in SEL for the below button response Host System State Button Action Powered on An...

Page 122: ...provided by the BMC for some of the network settings the values for some of the parameter data is defined as shown below DHCP In addition to the usual methods of obtaining an IP address the BMC provides a mode where it attempts to obtain an IP address from a DHCP server for a given period of time and if unsuccessful fails over to using a static IP address Parameter Parameter Data IP Address Source...

Page 123: ...I Set LAN Configuration Parameters command to set OEM Parameters to enable set MAC address to change MAC address Set ENABLE SET MAC this is defined in OEM Parameters as following OEM Parameters 194 C2h Data1 00h Set MAC address for BMC MAC0 01h Set MAC address for BMC MAC1 For example as following Step 1 Enable Set MAC address Ex ipmitool raw 0x0C 0x01 0x01 0xC2 0x00 Enable Set MAC for BMC MAC0 St...

Page 124: ...to drive 8 bit HEX GPIO to debug header described BMC post function would ready before system BIOS starts to send 1st POST code to port 80 BMC would access to POST code and record up to 256x POST codes OOB raw command can be used to retrieve last 20x POST code from BMC ...

Page 125: ...e LED at front side Power LED on is defined by the readiness of major run time power rails P12V P5V and P3V3 but NOT the readiness of all run time power rails for example CPU core power rail being ready is not required for Power LED on indication Power LED blinking is used as system identification The on time is different during power on and power off There are 4 states of Power system identificat...

Page 126: ...C for help 6 2 Firmware Update Every BIOS BMC file is unique for the motherboard it was designed for For Flash Utilities image downloads and information on how to properly use the Flash Utility with your motherboard 6 2 1 BIOS update You can do BIOS update via local or OOB This is an example of local BIOS update ...

Page 127: ...122 Here is the example of OOB BIOS update IP Your BMC IP C439_TGPSNTT_101 BIN The BMC image you received ...

Page 128: ...123 6 2 2 BMC update You can do BMC update via local or OOB Example of local BMC update Example of BMC update via OOB ...

Page 129: ...amming memory timing information 0x2E Memory initialization Configuring memory 0x2F Memory initialization other 0x30 Reserved for ASL see ASL Status Codes section below 0x31 Memory 0x32 CPU post memory initialization is started 0x33 CPU post memory initialization Cache initialization 0x34 CPU post memory initialization Application Processor s AP initialization 0x35 CPU post memory initialization B...

Page 130: ...s Recovery Progress Codes 0xF0 Recovery condition triggered by firmware Auto recovery 0xF1 Recovery condition triggered by user Forced recovery 0xF2 Recovery process started 0xF3 Recovery firmware image is found 0xF4 Recovery firmware image is loaded 0xF5 0xF7 Reserved for future AMI progress codes Recovery Error Codes 0xF8 Recovery PPI is not available 0xF9 Recovery capsule is not found 0xFA Inva...

Page 131: ... Boot Device Selection BDS phase is started 0x91 Driver connecting is started 0x92 PCI Bus initialization is started 0x93 PCI Bus Hot Plug Controller Initialization 0x94 PCI Bus Enumeration 0x95 PCI Bus Request Resources 0x96 PCI Bus Assign Resources 0x97 Console Output devices connect 0x98 Console input devices connect 0x99 Super IO Initialization 0x9A USB initialization is started 0x9B USB Reset...

Page 132: ...ion error 0xD3 Some of the Architectural Protocols are not available 0xD4 PCI resource allocation error Out of Resources 0xD5 No Space for Legacy Option ROM 0xD6 No Console Output Devices are found 0xD7 No Console Input Devices are found 0xD8 Invalid password 0xD9 Error loading Boot Option LoadImage returned error 0xDA Boot Option is failed StartImage returned error 0xDB Flash update is failed 0xD...

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