MIPS MIPS32 74K Series, Programming Manual

Page: 74 / 156

5.4 Shadow registers
Programming the MIPS32® 74K™ Core Family, Revision 02.14 74
If the CPU is not in EIC mode, this field reads zero.
In VI mode (no external interrupt controller,
Config3[VInt]
reads 1 and
Cause[IV]
has been set 1) the core sees only
eight possible interrupt numbers; the
SRSMap
register contains eight 4-bit fields defining the register set to use for
each of the eight interrupt levels.
If you are remaining with “classic” interrupt mode (
Cause[IV]
is zero), it’s still possible to use one shadow set for all
exception handlers — including interrupt handlers — by setting
SRSCtl[ESS]
non-zero.
SRSCtl[ESS]
: this writable field is the software-selected register set to be used for "all other" exceptions; that’s other
than an interrupt in VI or EIC mode (both have their own special ways of selecting a register set).
Unpredictable things will happen if you set
ESS
to a non-existent register set number (ie, if you set it higher than the
value in
SRSCtl[HSS]
.
SRSCtl[CSS,PSS]
:
CSS
is the register set currently in use, and is a read-only field. It’s set on any exception, replaced
by the value in
SRSCtl[PSS]
on an
eret
.
PSS
is the "previous" register set, which will be used following the next
eret
. It’s writable, allowing the OS to dis-
patch code in a new register set; load this value and then execute an
eret
. If you write a larger number than the total
number of implemented register sets the result is unpredictable.
You can get at the values of registers in the previous set using
rdpgpr
and
wrpgpr
.
Just a note:
SRSCtl[PSS]
and
SRSCtl[CSS]
are not updated by all exceptions, but only those which write a new
return address to
EPC
(or equivalently, those occasions where the exception level bit
Status[EXL]
goes from zero to
one). Exceptions where
EPC
is not written include:
• Exceptions occurring with
Status[EXL]
already set;
• Cache error exceptions, where the return address is loaded into
ErrorEPC
;
• EJTAG debug exceptions, where the return address is loaded into
DEPC
.
How new shadow sets get selected on an interrupt
In EIC mode, the external interrupt controller proposes a shadow register set number with each requested interrupt
(nonzero IPL). When the CPU takes an interrupt, the externally-supplied set number determines the next set and is
made visible in
SRSCtl[EICSS] until the next interrupt.
In VI mode (no external interrupt controller) the core sees only eight possible interrupt numbers; the SRSMap register
contains eight 4-bit fields, defining the register set to use for each of the eight interrupt levels, as shown in Figure 5.4 .
Figure 5.4 Fields in the SRSMap Register
In
SRSMap
, each of the
SSV7-0
fields has the shadow set number to be used when handling the interrupt for the cor-
responding
Cause[IP7-0]
bit. A zero shadow set number means not to use a shadow set. A number than the highest
valid set (as found in SRSCtl[HSS] ) has unpredictable results: don’t do that.
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
SSV7 SSV6 SSV5 SSV4 SSV3 SSV2 SSV1 SSV0
0 0 0 0 0 0 0 0