MIPS MIPS32 74K Series, Programming Manual

Page: 53 / 156

Memory map, caching, reads, writes and translation
53 Programming the MIPS32® 74K™ Core Family, Revision 02.14
The ContextConfig register is optional and its existence is denoted by the Config3
CTXTC
or Config3
SM
register fields.
Figure 3.16 shows the formats of the ContextConfig Register.
Figure 3.16 Fields in the ContextConfig register
VirtualIndex
is a mask of 0 to 32 contiguous 1 bits that cause the corresponding bits of the
Context
register to be writ-
ten with the high-order bits of the virtual address causing a TLB exception. Behavior of the processor is UNDE-
FINED if non-contiguous 1 bits are written into the register field.
It is permissible to implement a subset of the
ContextConfig
register, in which some number of bits are read-only and
set to one or zero as appropriate. It is possible for software to determine which bits are implemented by alternately
writing all zeroes and all ones to the register, and reading back the resulting values.
Table 3.7 describes some useful
ContextConfig
values.
31 0
VirtualIndex
Table 3.7 Recommended ContextConfig Values
Value
Page Table
Organization Page Size PTE Size Compliance
0x00000000007ffff0 Single Level 4K 64 bits/page REQUIRED
0x00000000003ffff8 Single Level 4K 32 bits/page RECOMMENDED
0x00000000007ffff8 Single Level 2K 32 bits/page RECOMMENDED
0x0000000000fffff8 Single Level 1K 32 bits/page RECOMMENDED