MIPS MIPS32 74K Series, Programming Manual

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Memory map, caching, reads, writes and translation
45 Programming the MIPS32® 74K™ Core Family, Revision 02.14
the first 512Mbytes of physical space, because then it will be accessible through the simple kseg0 “cached,
unmapped” region - with no need to set up specific TLB entries.
Because the SPRAM is close to the cache, it inherits some bits of cache housekeeping. In particular the
cache
instruction and the cache tag CP0 registers are used to provide a way for software to probe for and establish the size
of SPRAM
12
.
Probing for SPRAM configuration
The presence of scratchpad RAM in your core is indicated by a “1” bit in one or both of the CP0 Config[ISP,DSP] reg-
ister flags described in . The MIPS Technologies reference design requires that you can query the size of and adjust
the location of scratchpad RAM through “cache tags”.
To access the SPRAM “tags” (where the configuration information is to be found) first set the ErrCtl[SPR] bit (see
Section 3.4.17 “ErrCtl register” ).
Now a
cache Index_Load_Tag_D, KSE0
13
instruction fetches half the configuration information
into DTagLo , and a
cache Index_Load_Tag, KSE8
gets the other half (the “8” steps to the next
feasible tag location - an artefact of the 64-bit width of the cache interface.) The corresponding operations directed at
the primary I-cache read the halves of the I-side scratchpad tag, this time into
ITagLo . The “tag” for I-side and D-side
SPRAM appears in TagLo fields as shown in Figure 3.8 .
Where:
• base address[31:12]: the high-order bits of the physical base address of this chunk of SPRAM;
• En: enable the SPRAM. From power-up this bit is zero, and until you set it to 1 the SPRAM is invisible. The
En
bit is also visible in the second (size) configuration word — it can even be written there, but it’s not a good idea
to write the size word other than for far-out diagnostics;
• size of region in bytes/4KB: the number of page-size chunks of data mapped. If you take the whole 32 bits, it
returns the size in bytes (but it will always be a multiple of 4KB).
In some MIPS cores using this sort of tag setup there could be multiple scratchpad regions indicated by two or more
of these tag pairs. But the reference design provided with the 74K core can only have one I-side and one D-side
region.
You can load software into the ISPRAM using cacheops. Each pair of instructions to be loaded are put in the registers
IDataHi
/
IDataLo
, and then you use a
cache Index_Store_Data_I
at the appropriate index. The two data regis-
ters work together to do a 64-bit transfer. Note that the 74K core’s instruction memory really is 128 bits wide, so
you’ll need two cacheops to fully write a specific index. For a CPU configured big-endian the first instruction in
sequence is loaded into
IDataHi
, but for a CPU configured little-endian the first instruction is loaded into
IDataLo
.
12. What follows is a hardware convention which SoC designers are not compelled to follow; but MIPS Technologies recom-
mends designers to do SPRAM this way to ease software porting.
13. The instructions are written as if using C “ #define ” names from [m32c0 h]
Figure 3.8 SPRAM (scratchpad RAM) configuration information in TagLo
31 12 11 8 7 6 5 4 1 0
addr == 0 base address[31:12]
0
En 0
addr == 8 size of region in bytes/4KB
0
En 0