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Camera Link Transmitter HSMC Daughter Card User Manual 

 

Page 6 of 10 

differential  clock  inputs  capable  of  being  routed  to  a  PLL 

within the FPGA. 

 

 

The Microtronix 

Camera Link Tranmitter HSMC Daughter Card

 (PN: 

6287-01-01) is shown in Figure 1 below.  It provides two Camera Link 

MDR-26  female  connectors  (3M  –  14B26-SZLB-X00-OLC).  The  card 

can  be  configured  to  signal  PoCL  compatibility  to  frame  grabbers  that 

support  PoCL(Refer  to  notes  on  the  Camera  Link  board  schematics 

S6287 for more information).  The 26-pin CL connector pinout is shown 

in Table 1 below.  

 

 

Figure 1: Camera Link Transmitter HSMC Daughter Card 

 

Camera Link Connector 

The 26-pin Camera Link connectors are compliant with the Camera 

Link standard. The connector assignments are shown in the tables 

below.   Connector J1 (the connector on left) supports a Base interface 

and connector J2 (on the right) by default supports medium  or full 

configuration.   

 

Hardware 
Description 

Summary of Contents for HSMC Daughter Card

Page 1: ...4045 Meadowbrook Drive Unit 126 London ON Canada N6L 1E31 www microtronix com Microtronix Camera Link Transmitter HSMC Daughter Card USER MANUAL REVISION 1 0 ...

Page 2: ...e Description September 2012 Initial release Version 1 0 E mail Sales Information sales microtronix com Support Information support microtronix com Website General Website http www microtronix com Downloads http www microtronix com downloads Support FTP site http microtronix leapfile com Phone Numbers General 001 519 690 0091 Fax 001 519 690 0092 Document Revision History How to Contact Microtroni...

Page 3: ...nts Document Revision History 2 How to Contact Microtronix 2 E mail 2 Website 2 Phone Numbers 2 Card Features 4 Introduction 5 Kit Contents 5 Related Documentation 5 FPGA Host Board Compatibility 5 Hardware Description 6 Camera Link Connector 6 HSMC to Camera Link Connector Mapping 9 ...

Page 4: ...nk Transmitter HSMC Daughter Card User Manual Page 4 of 10 Dual Camera Link Transmitter connectors Supports single Base single Medium or single Full HSMC Type II or III differential LVDS interface Card Features ...

Page 5: ... documentation and board schematics Related Documentation The user may also want to refer to other Microtronix information including User Manuals for o Camera Link IP Core Design Kit o Camera Link IP Core Altera High Speed Mezzanine Card HSMC Specification FPGA Host Board Compatibility The card interfaces to Altera FPGA based development boards using differential LVDS signals which requires the us...

Page 6: ...oCL compatibility to frame grabbers that support PoCL Refer to notes on the Camera Link board schematics S6287 for more information The 26 pin CL connector pinout is shown in Table 1 below Figure 1 Camera Link Transmitter HSMC Daughter Card Camera Link Connector The 26 pin Camera Link connectors are compliant with the Camera Link standard The connector assignments are shown in the tables below Con...

Page 7: ...18 XClk LVDS Out CL X Channel Tx Clock FG0_n4 6 X3 LVDS Out CL X Channel Tx FG0_p4 19 X3 LVDS Out CL X Channel Tx FG0_n5 20 SerTC LVDS In Serial Data Transmitter FG0_p5 7 SerTC LVDS In Serial Data Transmitter FG0_n6 8 SerTFG LVDS Out Serial Data Receiver FG0_p6 21 SerTFC LVDS Out Serial Data Receiver FG0_n7 9 CC1 LVDS In User Selectable Input FG0_p7 22 CC1 LVDS In User Selectable Input FG0_n8 23 C...

Page 8: ...DS Out CL Y Channel Tx Clock FG1_p3_clk 18 YClk LVDS Out CL Y Channel Tx Clock FG1_n4 6 Y3 LVDS Out CL Y Channel Tx FG1_p4 19 Y3 LVDS Out CL Y Channel Tx FG1_n5 7 100 Ω LVDS In FG1_p5 20 TERMINATED LVDS In FG1_n6 8 Z0 LVDS Out CL Z Channel Tx FG1_p6 21 Z0 LVDS Out CL Z Channel Tx FG1_n7 9 Z1 LVDS Out CL Z Channel Tx FG1_p7 22 Z1 LVDS Out CL Z Channel Tx FG1_n8 10 Z2 LVDS Out CL Z Channel Tx FG1_p8...

Page 9: ...VDS_n31 55 FG0_n1 3 X1 P27 HSMC3_TXp1 V8 LVDS_p31 53 FG0_p1 16 X1 R26 HSMC3_TXn2 V5 LVDS_n29 61 FG0_n2 4 X2 R25 HSMC3_TXp2 V6 LVDS_p29 59 FG0_p2 17 X2 T27 HSMC3_TXn3 U5 LVDS_n27 67 FG0_n3 5 XClk T26 HSMC3_TXp3 U6 LVDS_p27 65 FG0_p3 18 XClk T24 HSMC3_TXn4 R6 LVDS_n25 73 FG0_n4 6 X3 T23 HSMC3_TXp4 R7 LVDS_p25 71 FG0_p4 19 X3 N30 HSMC3_RXn0 W1 LVDS_n36 50 FG0_n5 20 SerTC N29 HSMC3_RXp0 W2 LVDS_p36 48...

Page 10: ...HSMC3_TXn11 L6 LVDS_n11 121 FG1_n3 5 YClk AB25 HSMC3_TXp11 L7 LVDS_p11 119 FG1_p3 18 YClk AB26 HSMC3_TXn12 J5 LVDS_n9 127 FG1_n4 6 Y3 AC25 HSMC3_TXp12 J6 LVDS_p9 125 FG1_p4 19 Y3 Y28 HSMC3_RXn8 L3 LVDS_n18 104 FG1_n5 7 100 Ω AA28 HSMC3_RXp8 L4 LVDS_p18 102 FG1_p5 20 TERMINATED AD28 HSMC3_TXn13 M1 LVDS_n7 133 FG1_n6 8 Z0 AD27 HSMC3_TXp13 M2 LVDS_p7 131 FG1_p6 21 Z0 AE28 HSMC3_TXn14 G5 LVDS_n5 139 F...

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