miriac SBC-S32G-R3_User Manual
V 3.2
12/65
© MicroSys Electronics GmbH 2021
U-Boot 2020.04-4.1+g97081903ce (Mar 03 2021 - 07:18:34
+0000)
CPU: NXP S32G274A rev. 2.1.0
Reset cause: Power-On Reset
Model: MicroSys S32G274ASBC2
DRAM: 3.5 GiB
Board: Rev. 2
CA53 core 1 running.
CA53 core 2 running.
CA53 core 3 running.
All (4) cores are up.
MMC: FSL_SDHC: 0
Loading Environment from EEPROM... OK
DIP EEPROM[0]
PCIe0 CLK: 100MHz
PCIe1/SGMII CLK: 125MHz
RCON EEPROM WP: no
SEL SDHC: SDHC
BOOT MODE: RCON
PCIe0 clock 100MHz
Using external clock for PCIe0
Frequency 100Mhz configured for PCIe0
Configuring PCIe0 as RootComplex(x1)&SGMII [XPCS0
OFF(PCIex1), XPCS1 1G]
PCIe1 clock 125MHz
Using external clock for PCIe1
Frequency 125Mhz configured for PCIe1
Configuring PCIe1 as SGMII(x2) [XPCS0 2.5G, XPCS1 OFF]
PCIe0: Failed to get link up
Pcie0: LINK_DBG_1: 0x00000000, LINK_DBG_2: 0x00000800
(expected 0x000000d1)
DEBUG_R0: 0x0070b500, DEBUG_R1: 0x08200000
PCIe1: Not configuring PCIe, PHY not configured
In: serial
Out: serial
Err: serial
USB EHCI 1.00
Net: eth0: eth_eqos PFE: emac0: sgmii emac1: rgmii
emac2: rgmii , eth1: eth_pfeng
Hit any key to stop autoboot: 0
=>
3.4
Ordering Information
Ordering information can be found on the website
or contact your local sales representative.
