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VSC8221 Evaluation Board

VPPD-03471 VSC8221 User Guide Revision 1.0

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1.  

a.  

b.  

c.  

d.  

Figure 4 • Register List Window

Verify that the device is up and running by reading MII Register 0. It should read back 0x1040. Reading 
back “0000” or “FFFF” (all 0’s or all 1’s) indicates a problem.

To read or write the extended MII registers click on the ExtMII tab.

An initialization script may be used to configure multiple VSC8221 registers. The initialization script is 
simply a text file which contains a list of registers to be written. Select the Device item on the top pull 
down menu area and click on Load-All-Registers option. A pop-up window will appear. Navigate to and 
select the desired script to be loaded.

As per Section 31.1 of the datasheet, there are a number of internal registers that must be changed 
from their default value during device initialization. Use this method to initialize the device by loading 
“vsc8221_workaround31_1.txt” included in the GUI package under the Script/ directory. GUI Setup

4.4

Test Cases

4.4.1

CAT5 to 802.3z Serdes with Clause 37 AutoNeg Detection

After power-up or reset, the VSC8221 will operate at CAT5 to 802.3z Serdes with clause 37 Auto 
Negotiation Detection mode. An SFP loopback module enables MAC side SGMII loopback. 1G 
Ethernet received by the VSC8221 RJ-45 port is routed through the VSC8221 and looped back via 
SGMII through the SFP Electrical Loopback module.

Set up the copper Ethernet traffic source (e.g., IXIA or Smartbits).
Connect an Ethernet cable to an RJ-45.
Plug in a SFP loopback module.
Monitor the link-up bit in MII Register 1, bit 2 (MII 1.2), read twice to update. Traffic should now 
be flowing.

Summary of Contents for VSC8221

Page 1: ...VSC8221 User Guide VSC8221 Evaluation Board...

Page 2: ...Clk Option 4 3 1 7 Silabs Microcontroller 4 3 1 8 EEPROM Option 4 3 1 9 CMODE Pins 4 3 1 10 CLOCKOUT SMA 4 3 2 Software Requirements 4 4 Quick Start 5 4 1 Board Configuration 5 4 1 1 Clock and Reset 5...

Page 3: ...ision History The revision history describes the changes that were implemented in the document The changes are listed by revision starting with the most current publication 1 1 Revision 1 0 Revision 1...

Page 4: ...o includes Vitesse s VeriPHY Cable Diagnostics feature This document describes the operation of the VSC8221 Evaluation Board VSC8221EV The Quick Start section describes how to install and run the grap...

Page 5: ...en powered by a bench top supply the board may draw up to 3 A maximum module included 3 1 2 Copper Port RJ45 Connections The RJ45 copper media PHY port J1 uses a generic RJ45 jack with a discrete Puls...

Page 6: ...etail on how to program the desired operating condition parameters through the CMODE configuration bits and how to choose the value of each CMODE pull up or pull down resistor 3 1 10 CLOCKOUT SMA The...

Page 7: ...the PLL enable position and holding SW 2 in the 25 MHz position upon power up 4 1 2 Power Up Provide 5VDC to the board by plugging in the power cable included in the kit to J20 Two green LEDs should i...

Page 8: ...tart Programs Vitesse Semiconductor Corp VSC8221_Evaluation_System icons The initial window will detect the attached USB devices automatically The following figure shows a typical EVB Connection windo...

Page 9: ...the datasheet there are a number of internal registers that must be changed from their default value during device initialization Use this method to initialize the device by loading vsc8221_workaround...

Page 10: ...onitor the link up bit in MII Register 1 bit 2 MII 1 2 read twice to update Traffic should now be flowing 4 5 Useful Registers 4 5 1 Ethernet Packet Generator ExtMII 29E is the Ethernet Packet Generat...

Page 11: ...tion Board VPPD 03471 VSC8221 User Guide Revision 1 0 9 5 Additional Information For any additional information or questions regarding the device s mentioned in this document contact your local sales...

Page 12: ...etermine suitability of any products and to test and verify the same The information provided by Microsemi hereunder is provided as is where is and with all faults and the entire risk associated with...

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