CAN Controller
UG0331 User Guide Revision 15.0
437
12.1.3
Transmit Path
•
32 transmit message holding registers with programmable priority arbitration
•
Message abort command
•
Single-shot transmission (SST); no automatic retransmission upon error or arbitration loss
12.1.4
EDAC
An internal 256 x 32 RAM in the CAN controller is EDAC protected. EDAC configurations and error
counters related to the CAN are maintained in MSS system registers. For example, to enable or disable
the EDAC component of the CAN, set the CAN_EDAC_EN bit (6th bit in the SYSREG EDAC_CR
register) to 1. By default, EDAC is disabled (CAN_EDAC_EN is set to 0). Refer to
for more information.
After power-up, the internal SRAM is not initialized and any READ to the memory location would result in
an ECC error if EDAC is enabled. To initialize the SRAM, you can put the CAN controller into SRAM Test
mode, initialize the SRAM, and enable the EDAC. If SECDED is enabled, Microsemi recommends that
the CAN controller be put into SRAM Test mode and the RAM initialized with user defined known data
before operation so that a future read or an uninitialized address does not trigger a SECDED error. Refer
to the
page 448 for more details on how to put the CAN controller into SRAM Test mode.
12.1.5
Enable or Disable Control
The CAN controller can be enabled or disabled using the MSS configurator in Libero SoC, depending on
the application needs. When it is disabled, the CAN controller is held in reset (lowest power state). Refer
to the
page 446 for more information on how to enable or disable the CAN
controller using Libero SoC.
12.1.6
System Dependencies
12.1.6.1 Reset
The CAN controller resets to zero on power-up and is held in reset until enabled, as shown in
Controller Soft Reset Bit in the SOFT_RESET_CR Register,
page 452 in the SOFT_RESET_CR register.
The CAN controller can be reset by writing to CAN_SOFTRESET (bit13) of the SOFT_RESET_CR
register. The SOFT_RESET_CR register is located in the SYSREG block. Refer to the
page 670 for more details.
12.2
Functional Description
12.2.1
CAN Controller Interface Signals
This section describes the CAN bus interfaces. The external interface signals connecting the
SmartFusion2 device to an off-chip CAN transceiver are listed in the following table.
Table 435 •
CAN BUS Interface
Signal Name
Direction Description
RX
Input
CAN bus receive signal. This signal connects to the receiver bus of the external driver.
TX
Output
CAN bus transmit signal. This signal connects to the external driver.
TX_EN_N
Output
External driver enable control signal
This signal is used to enable or disable an external CAN transceiver.
TX_EN_N is asserted when the CAN controller is stopped or if the CAN state is bus-off
(shut down completely).