Ethernet MAC
UG0331 User Guide Revision 15.0
399
Minimal configuration, required for MAC to make it functional in 1000 Mbps mode of operation, is given
below:
CFG1= 32'h0000_0035 //Rx/Tx flow control enable, Rx/Tx-Enable
CFG2 = 32'h0000_7202 //Preamble=7, byteMode, CRC-enable
STATION_ADDRESS1 = 32'hA5A4_A3A2 //Station Address 1-4
STATION_ADDRESS2 = 32'hA1A0_0000 //Station Address 5-6
FIFO_CFG0 = 32'h0000_FF00 //Enable FIFO transmit and receive modules
FIFO_CFG3 = 32'h007F_FFFF // Tx-FIFO high watermark=128
11.8
EMAC Register Bit Definitions
The following tables are the bit definitions of the registers present in EMAC.
Table 339 •
DMA_TX_CTRL
Bit
Number
Name
Reset
Value
Description
[31:1]
Reserved
0x0
Reserved
0
Transmit control
0x0
TxEnable: Setting this bit enables DMA transmit packet transfers.
The bit is cleared by the built-in DMA controller whenever it encounters a
Tx Underrun or Bus Error state.
Table 340 •
DMA_TX_DESC
Bit
Number
Name
Reset
Value
Description
[31:2]
Top 30 bits of
Descriptor
Address
0x0.
When TxEnable is set by the host, the built-in DMA controller reads this
register to discover the location in the host memory of the first transmit
packet descriptor.
[1:0]
Ignored by the
DMA controller
0x0
All descriptors are 32-bit aligned in the host memory.
Table 341 •
DMA_TX_STATUS
Bit Number
Name
Reset Value Description
[31:24]
Reserved
0x0
Reserved
[23:16]
TxPktCount
0x0
The 8-bit transmit packet counter that is incremented whenever the
built-in DMA controller successfully transfers a packet, and is
decremented whenever the host writes a '1' to bit '0' in this register.
[16:4]
Reserved
0x0
Reserved
3
BusError
0x0
When set, this indicates that a host slave split, retry or error
response is received by the DMA controller.
2
Reserved
0x0
Reserved
1
TxUnderrun
0x0
Set whenever the DMA controller reads a '1' for the empty flag in
the descriptor.
0
TxPktSent
0x0
When set, this indicates that one or more packets have been
successfully transferred.
Writing a '1' to this bit reduces the TxPktCount value by one. The bit
is cleared whenever TxPktCount is zero.