Ethernet MAC
UG0331 User Guide Revision 15.0
382
11.4.1
Transmit Operation
1.
Before any packet can be transmitted, a group of Tx descriptors needs to be set up to define the ring
buffer used for transmit operations.
The start addresses set for the different segments of the ring buffer are required to be word aligned
and should be spaced to give segments of equal size, each able to handle a packet of the maximum
size to be transferred.
The packet size component of transmit descriptors should initially be written to have ‘1’ in bit 31,
which is the empty flag to indicate that the ring buffer does not currently contain any valid data.
2.
The least significant four bits of the DMA interrupt mask register are set to specify which Tx DMA
events cause a DMA interrupt to be generated.
3.
The data for one or more transmit packets should then be placed in contiguous segments of the ring
buffer. The PacketSize component of the descriptor associated with these segments amended both
to record the size of the packet placed in the buffer and to set the Empty Flag to ‘0’ to indicate the
presence of valid data.
4.
The location of the descriptor, which acts as the entry point in the Tx ring buffer, is written in the DMA
Tx descriptor register.The DMA transfer of the transmit packets are enabled by writing a ‘1’ to the bit
0 of the DMA Tx control register, which is Tx enable bit.
5.
The built-in DMA controller then reads the DMA Tx descriptor register to discover the location of the
first Tx descriptor. The Tx descriptor is read to check the validity of the associated packet which is
indicated by the empty flag, the start address of the packet to be transmitted, and its size.
If the empty flag is ‘1’ then the descriptor is not associated with valid data. The DMA controller termi-
nates the sequence of transmit packet transfers, set the TxUnderrun bit in the DMA Tx Status regis-
ter and clear the TxEnable bit in the DMA Tx Control register. The TxUnderrun bit in the DMA Tx
Status register is set whenever DMA controller reads a ‘1’ in the empty flag of the Tx Descriptor
being processed.
[20:16]
FTPP Overrides
0x0
The 5-bit field containing the FIFO transmit per-packet
override flags signaled to the A-MCXFIFO during the packet
transmission. The bits are encoded as follows:
20: FIFO transmit control frame flag.
19:18: FIFO transmit per-packet pad mode flag.
0x0: Do not pad transmit frame.
0x1: Pad all frames to 64 bytes and append FCS to all frames.
0x2: Reserved.
0x3: Reserved.
17: FIFO transmit per-packet generate FCS flag.
16: FIFO transmit per-packet enable flag.
[15:12]
Reserved
0x0
Reserved.
[11:0]
PacketSize
0x0
For the transmit operations, the 12-bit field gives the size of
packet to be transferred in bytes.
In the receive operations, the DMA controller writes the
number of bytes received to this field.
The value of this field prior to the transfer being made is
ignored.
Table 326 •
Next Descriptor
Bit Number Name
Reset Value
Description
[31:2]
Next Descriptor[31:2]
0x0
The built-in DMA controller reads this register to discover the
location in the host memory of the descriptor for the next
packet in the sequence. The descriptors should form a closed
linked list.
[1:0]
Next Descriptor[1:0]
0x0
All descriptors are 32-bit aligned in the host memory.
Table 325 •
Packet Size
(continued)