AHB Bus Matrix
UG0331 User Guide Revision 15.0
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supports remapping of an eNVM segment to location 0x00000000 in the memory map seen by masters
in the FPGA fabric with the ENVM_REMAP_FAB_CR control register.
The ENVM_REMAP_FAB_CR control register configures where ENVM is mapped in fabric space.There
is no eSRAM remap for fabric masters. Therefore, a fabric master must always access eSRAM from its
location described in
The following figure gives an example representation of the eNVM remap of a soft processor
implemented in FPGA fabric and remapped to a virtual address 0x00000000, even though its physical
address starts at 0x60003000.
Figure 116 •
Virtual eNVM View for Soft Processor
7.1.4.3
DDR Memory Map
Although up to 4 Gbytes of DDR is supported by the system, only 1 GB of this is accessible at one time
from the Cortex-M3 processor or MSS masters via the AHB bus matrix. The HPDMA and DDR_FIC can
access all 4 Gbytes at default settings. In order to make a particular region of DDR visible to the Cortex-
M3 processor firmware or another non-HPDMA MSS master, it is necessary to configure the appropriate
DDR mapping registers in the MSS system registers.
7.1.4.4
DDR Remap
In default mode, the Cortex-M3 processor firmware boots from eNVM. However, as shown in the
following figure, it is also possible to get the firmware to boot from DDR by re-mapping DDR to location
zero. Code shadowing is supported to facilitate this. User boot firmware, located in eNVM, must copy an
executable image from external flash memory (serial or parallel) to external DDR memory, then jump to
the application entry point in external DDR memory.
In DDR remap mode, the total available cacheable region (512 Mbytes) can be configured to
128 Mbytes, 256 Mbytes, or 512 Mbytes. In the case of a 128 Mbyte cacheable size, the entire
512 Mbytes is divided into four cacheable regions of 128 Mbytes each, and one of the four regions will be
selected as per configuration. Similarly for 256 Mbytes, one of the two cacheable regions (512 Mbytes
cacheable region split to two 256 Mbyte regions) will be selected as per configuration. These selections
can be configured using the DDRB_NB_ADDR_CR and DDRB_NB_SIZE_CR registers.
Physical View of eNVM
(FPGA Fabric)
Virtual eNVM
(FPGA Fabric
Master View)
0x60000000
0x6FFFFFFF
eNVM remap
(after chip boot)
0x60001FFF
0x60002000
0x00000000
Firmware n
Firmware for
Soft Processor
in FPGA Fabric
0x60002FFF
0x60003000
0x60003FFF
Firmware for
Soft Processor
in FPGA Fabric
Firmware2
for Cortex-M3
Microcontroller
Firmware1
for Cortex-M3
Microcontroller