4.
On-chip Debugging
4.1
Introduction
On-chip Debugging
An on-chip debug module is a system allowing a developer to monitor and control execution on a device from an
external development platform, usually through a device known as a
debugger
or
debug adapter
.
With an OCD system the application can be executed whilst maintaining exact electrical and timing characteristics in
the target system, while being able to stop execution conditionally or manually and inspect program flow and
memory.
Run Mode
When in Run mode, the execution of code is completely independent of the Power Debugger. The Power Debugger
will continuously monitor the target device to see if a break condition has occurred. When this happens the OCD
system will interrogate the device through its debug interface, allowing the user to view the internal state of the
device.
Stopped Mode
When a breakpoint is reached, the program execution is halted, but some I/O may continue to run as if no breakpoint
had occurred. For example, assume that a USART transmit has just been initiated when a breakpoint is reached. In
this case the USART continues to run at full speed completing the transmission, even though the core is in Stopped
mode.
Hardware Breakpoints
The target OCD module contains a number of Program Counter comparators implemented in the hardware. When
the Program Counter matches the value stored in one of the comparator registers, the OCD enters Stopped mode.
Since hardware breakpoints require dedicated hardware on the OCD module, the number of breakpoints available
depends upon the size of the OCD module implemented on the target. Usually one such hardware comparator is
‘reserved’ by the debugger for internal use.
Software Breakpoints
A software breakpoint is a
BREAK
instruction placed in program memory on the target device. When this instruction is
loaded, program execution will break and the OCD enters Stopped mode. To continue execution a “start” command
has to be given from the OCD. Not all Microchip devices have OCD modules supporting the
BREAK
instruction.
4.2
SAM Devices with JTAG/SWD
All SAM devices feature the SWD interface for programming and debugging. In addition, some SAM devices feature
a JTAG interface with identical functionality. Check the device data sheet for supported interfaces of that device.
4.2.1
ARM CoreSight Components
Microchip ARM Cortex-M based microcontrollers implement CoreSight compliant OCD components. The features of
these components can vary from device to device. For further information consult the device’s data sheet as well as
CoreSight documentation provided by ARM.
4.2.2
JTAG Physical Interface
The JTAG interface consists of a 4-wire Test Access Port (TAP) controller that is compliant with the IEEE
®
1149.1
standard. The IEEE standard was developed to provide an industry-standard way to efficiently test circuit board
connectivity (Boundary Scan). Microchip AVR and SAM devices have extended this functionality to include full
Programming and On-chip Debugging support.
Power Debugger
On-chip Debugging
©
2020 Microchip Technology Inc.
User Guide
DS40002201A-page 53
