PIC24FV16KM204 FAMILY
DS33030A-page 268
Advance Information
2013 Microchip Technology Inc.
TABLE 27-1:
THERMAL OPERATING CONDITIONS
Rating
Symbol
Min
Typ
Max
Unit
Operating Junction Temperature Range
T
J
-40
—
+140
°C
Operating Ambient Temperature Range
T
A
-40
—
+125
°C
Power Dissipation:
Internal Chip Power Dissipation:
P
INT
= V
DD
x (I
DD
–
I
OH
)
P
D
P
INT
+ P
I
/
O
W
I/O Pin Power Dissipation:
P
I
/
O
=
({V
DD
–
V
OH
} x I
OH
) +
(V
OL
x I
OL
)
Maximum Allowed Power Dissipation
P
DMAX
(T
J
– T
A
)/
JA
W
TABLE 27-2:
THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol
Typ
Max
Unit
Notes
Package Thermal Resistance, 20-Pin SPDIP
JA
62.4
—
°C/W
Package Thermal Resistance, 28-Pin SPDIP
JA
60
—
°C/W
Package Thermal Resistance, 20-Pin SSOP
JA
108
—
°C/W
Package Thermal Resistance, 28-Pin SSOP
JA
71
—
°C/W
Package Thermal Resistance, 20-Pin SOIC
JA
75
—
°C/W
Package Thermal Resistance, 28-Pin SOIC
JA
80.2
—
°C/W
Package Thermal Resistance, 28-Pin QFN
JA
32
—
°C/W
Package Thermal Resistance, 44-Pin QFN
JA
29
—
°C/W
Package Thermal Resistance, 48-Pin UQFN
JA
41
—
°C/W
Note 1:
Junction to ambient thermal resistance, Theta-
JA
(
JA
) numbers are achieved by package simulations.
TABLE 27-3:
DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 1.8V to 3.6V (PIC24F16KMXXX)
2.0V to 5.5V (PIC24FV16KMXXX)
Operating temperature
-40°C
T
A
+85°C for Industrial
-40°C
T
A
+125°C for Extended
Param
No.
Symbol
Characteristic
Min
Typ
(
Max Units
Conditions
DC10
V
DD
Supply Voltage
1.8
—
3.6
V
For PIC24F devices
2.0
—
5.5
V
For PIC24FV devices
DC12
V
DR
RAM Data Retention
Voltage
(
1.6
—
—
V
For PIC24F devices
1.8
—
—
V
For PIC24FV devices
DC16
V
POR
V
DD
Start Voltage
to Ensure Internal
Power-on Reset Signal
V
SS
—
0.7
V
DC17
SV
DD
V
DD
Rise Rate
to Ensure Internal
Power-on Reset Signal
0.05
—
—
V/ms 0-3.3V in 0.1s
0-2.5V in 60 ms
Note 1:
Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2:
This is the limit to which V
DD
can be lowered without losing RAM data.
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