1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
D
D
C
C
B
B
A
A
3
of
4
P
IC
18
F
47
K
42
C
u
ri
os
it
y
N
an
o
09
.0
5.
20
19
P
IC
18
F
47
K
42
_C
uri
os
it
y_
N
an
o_
D
eb
ug
ger
.Sc
hD
oc
Proj
ect
Tit
le
PCB
Ass
emb
ly N
umb
er:
PCBA
Revis
ion:
File:
PCB
Numb
er:
PC
B
Re
vi
si
on
:
Desig
ned
with
Dra
wn
By
:
M
ic
ro
ch
ip
N
or
w
ay
She
et
Tit
le
Debugg
er
Engineer:
TF, H
N
A08-2985
2
Size
A
3
A09-3244
2
Page:
Date:
Alt
ium
.co
m
DEBUGGE
R USB
MICRO-B
CONNEC
TOR
GND
USBD_P
USBD_N
100n
C107
100n
C108
RX
TX
UART
C
D
C
_
U
A
R
T
1k
R107
VCC_P3V3
100n
C104
GND
SRST
STATUS_LED
SHIELD
VBUS
VCC_P3V3
GND
TP100
Test
poin
t Ar
ray
1
2
3
4
5
6
7
8
9
1
0
TCK
TDO
TMS
Vsup
TDI
GND
TRST
SRST
VTref
GND
J102
GND
4.
7u
F
C100
D
B
G
0
DBG0
2
1
GRE
EN
LED
SML-P12MTT86R
D100
V
B
U
S
1
D
-
2
D
+
3
G
N
D
5
S
H
I
E
L
D
1
6
S
H
I
E
L
D
2
7
I
D
4
S
H
I
E
L
D
3
8
S
H
I
E
L
D
4
9
MU-MB0142AB2-269
J105
P
A
D
3
3
P
A
D
P
A
0
0
1
P
A
0
1
2
P
A
0
2
3
P
A
0
3
4
GN
D
10
VD
DA
NA
9
P
A
0
4
5
P
A
0
5
6
P
A
0
6
7
P
A
0
7
8
PA
08
11
PA
09
12
PA
10
13
PA
11
14
PA
14
15
PA
15
16
P
A
1
6
1
7
P
A
1
7
1
8
P
A
1
8
1
9
P
A
1
9
2
0
P
A
2
2
2
1
U
S
B
_
S
O
F
/
P
A
2
3
2
2
U
S
B
_
D
M
/
P
A
2
4
2
3
U
S
B
_
D
P
/
P
A
2
5
2
4
PA
27
25
RE
SE
TN
26
PA
28
27
GN
D
28
VD
DC
OR
E
29
VD
DI
N
30
SW
DC
LK
/P
A3
0
31
SW
DI
O/
PA
31
32
SAMD21E18A-MUT
U100
V
O
U
T
1
V
O
U
T
2
GN
D
3
E
N
4
V
I
N
6
N
C
5
EP
7
MIC5
528-3
.3YM
T
U101
VCC_P3V3
GND
USBD_P
USBD_N
GND
1u
C106
VCC_MCU_CORE
VCC_P3V3
VCC_P3V3
GND
4.
7u
F
C100
V
O
U
T
1
V
O
U
T
2
GN G G
D
3
E
N
4
V
I
N
6
N
C
5
EP
7
MIC5
528-3
.3YM
T
U101
VCC_P3V3
GND
2.
2u
F
C101
GND
74LVC1T45FW4-7
V
C
C
A
1
V
C
C
B
6
A
3
G
N
D
2
D
I
R
5
B
4
U103
VCC_P3V3
GND
74LVC1T45FW4-7
V
C
C
A
1
V
C
C
B
6
A
3
G
N
D
2
D
I
R
5
B
4
U104
VCC_P3V3
GND
74LVC1T45FW4-7
V
C
C
A
1
V
C
C
B
6
A
3
G
N
D
2
D
I
R
5
B
4
U105
VCC_P3V3
GND
GND
GND
GND
GND
74LVC1T45FW4-7
V
C
C
A
1
V
C
C
B
6
A
3
G
N
D
2
D
I
R
5
B
4
U107
VCC_P3V3
GND
D
B
G
2
DBG3_CTRL
S1_0_TX
S1_1_RX
S0_2_TX
DAC
VTG_ADC
RESERVED
S0_3_CLK
DBG0_CTRL
CDC_TX_CTRL
BOOT
DEB
UGG
ER
POW
ER/
STA
TUS
LE
D
1k
R107
VCC_P3V3
2
1
GRE
EN
LED
SML-P12MTT86R
D100
E
N
1
B
Y
P
6
V
O
U
T
4
G
N
D
2
V
I
N
3
N
C
/
A
D
J
5
G
N
D
7
MIC5353
U102
VCC_VBUS
100n
C102
GND
GND
47k
R101
27k
R104
GND
33k
R106
GND
E
N
1
B
Y
P
6
V
O
U
T
4
G
N
D
2
V
I
N
3
N
C
/
A
D
J
5
G
N
D
7
MIC5353
U102
VCC_VBUS
100n
C102
GND
GND
47k
R10
1
27k
R10
4
GND
33k
R106
2.
2u
F
C103
GND
1k1k
R108
J100
VCC_LEVEL
VCC_REGULATOR
74LVC1T45FW4-7
V
C
C
A
1
V
C
C
B
6
A
3
G
N
D
2
D
I
R
5
B
4
U106
VCC_P3V3
GND
D
B
G
1
CDC_RX
CDC_TX
D
B
G
3
DBG1_CTRL
DEBUGGER REGULATOR
REG_ENABLE
REG_ENABLE
47k
47k
R103
VCC_LEVEL
VCC_LEVEL
VCC_LEVEL
VCC_LEVEL
VCC_LEVEL
47k
47k
R102
47k
47k
R105
SWCLK
GND
47k
47k
R100
GND
DBG2
S0_0_RX
DBG1_CTRL
DBG0_CTRL
GND
DBG3
OPEN
DRAIN
TAR
GET
AD
JU
STA
BLE
RE
GUL
ATO
R
SRST
100n
C104
GND
SRST
VCC_P3V3
GND
Test
poin
t Ar
ray
1
2
3
4
5
6
7
8
9
1
0
TCK
TDO
TMS
Vsup
TDI
GND
TRST
SRST
VTref
GND
J102
SWCLK
DE
BU
GGE
R
TES
TPO
IN
Ts
DBG2_CTRL
VOFF
CDC_RX_CTRL
47k
47k
R109
DBG1
CDC_TX_CTRL
CDC_RX_CTRL
SWCLK
REG_ADJUST
DBG2_GPIO
DBG3_CTRL
DBG2_CTRL
UPDI
UPDI
GPIO
GPIO
RESET
Signal
DBG0
DBG1
DBG2
DBG3
ICSP
Interface
DAT
CLK
GPIO
MCLR
DBG3
CD
C
TX
CD
C
RX
UAR
T R
X
UAR
T
TX
UAR
T R
X
UAR
T
TX
TARGET
TARGET
1k1k
R110
VBUS_ADC
DMN65D8LFB
1
2
3
Q101
VCC
-
-
I
D
_
S
Y
S
V
O
F
F
1k
R112
VCC_P3V3
I
D
_
S
Y
S
I
D
_
S
Y
S
1k
R11
2
VCC_P3V3
VTG_ADC
DAC
MIC94163
V
I
N
B
2
V
O
U
T
A
1
V
I
N
A
2
E
N
C
2
G
N
D
C
1
V
O
U
T
B
1
U108
GND
ID_SYS
VTG_EN
VTG_EN
VBUS_ADC
SWDIO
ID_SYS
TP101
GND
SWDIO
VOFF
47k
47k
R111
GND
ID
PIN
MC36213
F100
VCC_VBUS
VCC_VBUS
VCC_EDGE
J101
VCC_TARGET
Pro
gram
mi
ng c
onn
ect
or
fo
r
fa
ct
or
y
pr
og
ra
mm
in
g
of
Debugger
MIC5528:
V
in
: 2.
5V
to
5
.5V
Vo
ut
: Fi
xe
d
3.
3V
Ima
x:
500
mA
Dr
op
ou
t:
2
60
mV
@
5
00
mA
Adju
stab
le o
utp
ut a
nd
limi
tat
ion
s:
-
Th
e
on
bo
ar
d
de
bug
ge
r
ca
n
ad
ju
st
the
o
ut
put
v
ol
ta
ge
o
f
th
e
re
gu
la
to
r
be
tw
ee
n
1.
25
V
and
5
.1
V
to
the
tar
ge
t.
-
Th
e
le
ve
l sh
if
te
rs
h
av
e
a
mi
ni
ma
l vo
lt
ag
e
le
ve
l of
1
.6
5V
a
nd
w
il
l li
mi
t th
e
mi
ni
mu
m
op
er
at
in
g
vo
lt
ag
e
al
lo
we
d
fo
r
th
e
ta
rg
et
to
sti
ll
a
llo
w c
omm
un
ica
ti
on.
-
Th
e
ou
tp
ut
s
wi
tc
h
ha
s
a
mi
ni
ma
l vo
la
te
ge
lev
el
o
f
1.
70
V
an
d
wi
ll
lim
it
the
m
in
im
um
v
ol
ta
ge
d
el
iv
er
ed
to
th
e
ta
rg
et
.
-
Fi
rm
wa
re
c
on
fi
gu
ra
ti
on
w
il
l li
mi
t th
e
vo
lt
ag
e
ra
ng
e
to
b
e
wi
th
in
the
the
tar
ge
t sp
ec
if
ic
at
io
n.
-
Fi
rm
wa
re
f
ee
db
ac
k
lo
op
w
il
l ad
ju
st
the
o
ut
pu
t vo
lt
ag
e
ac
cu
ra
cy
to
wi
th
in
0.
5%
.
PTC
Re
sett
abl
e fu
se:
Hol
d c
urr
ent
: 500
mA
Tri
p c
urr
en
t:
100
0mA
MIC5353:
Vi
n:
2.
6V
to
6V
Vo
ut
: 1.
25V
to
5
.1
V
Ima
x:
500
mA
Dr
op
ou
t (t
yp
ic
al
):
5
0m
V@
15
0m
A,
1
60
mV
@
5
00
mA
Acc
ura
cy:
2%
in
iti
al
The
rma
l shu
tdo
wn
an
d c
urr
en
t l
im
it
Ma
xi
mu
m
ou
tp
ut
v
ol
ta
ge
is
li
mi
te
d b
y
th
e
in
pu
t vo
lt
ag
e
an
d
th
e
dr
op
ou
t vo
lt
ag
e
in
the
r
eg
ul
at
or
.
(V
m
ax
=
Vi
n
-
dr
op
ou
t)
J100:
Cu
t-
st
ra
p
us
ed
f
or
f
ul
l sep
ar
at
io
n
of
tar
ge
t po
we
r
fr
om
the
lev
el
s
hi
ft
er
s
an
d
on
-b
oa
rd
r
eg
ul
at
or
s.
-
Fo
r
cu
rr
en
t me
as
ur
em
en
ts
u
si
ng
a
n
ex
te
rn
al
p
ow
er
s
up
ply
, th
is
s
tr
ap
c
ou
ld
b
e
cu
t fo
r
mo
re
ac
cu
ra
te
m
ea
su
re
me
nt
s.
L
ea
ka
ge
b
ac
k
th
ro
ug
h
th
e
sw
it
ch
is
in
the
m
ic
ro
a
mp
er
e
ra
ng
e.
J101:
Th
is
is
fo
ot
pr
in
t fo
r
a
1x
2
10
0m
il
p
it
ch
p
in
-h
ea
de
r
th
at
c
an
b
e
us
ed
f
or
e
as
y
cu
rr
en
t me
as
ur
em
en
t
to
the
tar
ge
t mi
cr
oc
on
tr
ol
le
r
an
d
th
e
LE
D
/ Bu
tt
on
. To
u
se
the
f
oo
tp
ri
nt
:
-
Cu
t th
e
tra
ck
be
tw
ee
n
th
e
ho
le
s,
a
nd
m
ou
nt
a
p
in
-h
ead
er
PIC18F47K42 Curiosity Nano
Appendix
©
2019 Microchip Technology Inc.
User Guide
DS50002899B-page 21
