Appendix: 1G Ethernet BASE-T and BASE-X Using Transceiver
Microsemi Proprietary DG0799 Demo Guide Revision 3.0
34
The following points summarize the 1G Ethernet BASE-T and BASE-X designs:
•
The Mi-V soft processor is used to configure the PHY registers (using MDIO interface), MAC
Configuration and Management registers. User can also implement a fabric logic or any other soft
processor to implement these functions.
•
The MAC IP is configured in the ten bit interface mode (TBI).
•
In BASE-T, the management block of the MAC IP auto-negotiates with the on-board PHY as per
Clause 28 of the IEEE802.3z standard. The PHY auto-negotiates with the link partner.
•
In BASE-X, the management block of the MAC IP auto-negotiates with the link partner as per
Clause 37 of the IEEE802.3z standard.
•
The auto-negotiation (AN) functions are defined in the MAC Management registers 04h to 08h. The
bit field formats of these registers are different for BASE-T and BASE-X. For more information about
the bit field formats of the AN registers, see
The following table lists the AN registers.
The following registers are common in BASE-T and BASE-X modes:
•
Control register at address 0x00
•
Status register at address 0x01
Registers 0x04, 0x05, 0x06, 0x07, and 0x08 are based on the configuration.
•
XCVR is configured to operate at 1250 Mbps. For more information about XCVR configuration, see
•
The user data from MAC (CoreTSE non-AHB) is provided on a 32-bit parallel bus.
7.2
Transceiver Configuration
For 1G Ethernet BASE-T and BASE-X, the transceiver block is configured for 1.25 Gbps data rate.
page 35 shows the configuration of the transceiver block in Libero SoC design suite. The
following table lists the transceiver configuration.
Table 5 •
AN Registers
Register
Description
04h
AN Advertisement
05h
AN Link Partner
Base Page Ability
06h
AN Expansion
07h
AN Next Page
Transmit
08h
AN Link Partner
Ability Next Page
Table 6 •
XCVR Configuration
Parameters
Settings
Number of lanes
1
Data Rate
1250 Mbps
PMA
TX clock division factor
4
TX PLL base data rate
5000 Mbps
TX PLL bit clock frequency
2500 Mbps
CDR lock mode
lock to data
CDR reference clock source
Dedicated
