PolarFire FPGA 1G Ethernet Loopback Using IOD CDR
Microsemi Proprietary DG0799 Demo Guide Revision 3.0
16
2.4
Clocking Structure
In the demo design, there are two clock sources—the on-board 50 MHz oscillator and the on-board
ZL30364 clock generation hardware.
•
On-board 50 MHz oscillator:
This oscillator drives the PLL that generates an 80-MHz clock for the
Mi-V soft processor and peripherals. In this design, Mi-V processor runs at 80 MHz.
•
On-board ZL 30364 clock generation hardware:
This hardware generates the reference clocks for
the VSC PHY, the IOD CDR fabric module, and CoreTSE.
page 16 shows the clocking structure of the demo design.
Figure 15 •
Clocking Structure
PF_CCC_0
Onboard 50 MHz Oscillator
Onboard ZL 30364
Clock generaion hardware
Mi-V
softprocessor
Clock Source 1
Clock Source 2
High-Speed Bank
Clocks for CDR
625MHz
50 MHz
80 MHz
CoreSPI_0
OUT0_F
ABCLK_0
Pf_sram_0
HCLK
CLK
MTXCLK
MRXCLK
PCLK
125 MHz
125 MHz
Onboard
VSC8575
PHY
125 MHz
PCLK
0,90,180,270
PF_IOD_CDR_CCC
PF_IOD_CDR
RX_CLK_R
TXCLK
RXCLK
CoreTSE
TBI_TX_CLK
TBI_RX_CLK
TX_CLK_G_TO_CDR
