KSZ8061MNX Evaluation Board User’s Guide
DS50002449A-page 18
2016 Microchip Technology Inc.
2.4
POWER
The evaluation board requires a DC supply at barrel connector J8. A jumper must be
installed on pins 2-3 of JP3. The voltage requirement is 4.5V to 14V. The current
requirement is 200 mA.
An alternate power connection is available at the 10-pin management header J7. This
is intended to allow the board to be powered from a USB cable such as the FTDI
C232HM-EDHSL-0. When supplying power via header J7, a jumper must be installed
on pins 1-2 of JP3 (labeled “5V_HDR”).
A noise filtering choke is provided on the J8 connector, but not on the J7 power pins.
Therefore, J8 is the preferred power connector when testing KSZ8061 performance.
2.5
CLOCKING
The KSZ8061 utilizes a 25 MHz reference clock. There are two options for supplying
this clock: crystal or external clock. If the second PHY (KSZ8081, U2) is used, then the
two PHYs must be synchronized and the only clocking option is to clock both PHYs
from the same external clock source.
1.
External clock (default configuration). The external clock source is a Microchip
PL135-27 (U3), which drives the same 25 MHz clock to both PHYs. When using
this clock source, the KSZ8061 crystal (Y1) must not be connected from the
KSZ8061. This is done either by removing R91 and R92, or by removing Y1, refer
to
.
FIGURE 2-6:
EXTERNAL CLOCK OPTION
2.
Crystal. Crystal Y1 can be connected directly to the KSZ8061, which has an
on-chip oscillator. Install resistors R91 and R92, and remove resistor R62. To
fully turn off the external clock (U3), remove R63. This mode can be used only
when the KSZ8061 and KSZ8081 are not used in back-to-back configuration.
KSZ8061MNX (U1)
XI
XO
R91 / DNI
R92 / DNI
R62 / 0
ȍ
PL135-27 (U3)
Y1
CLK1
XI
KSZ8081MNX (U2)
CLK0
