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KSZ8061MNX EVALUATION
BOARD USER’S GUIDE
2016 Microchip Technology Inc.
DS50002449A-page 11
Chapter 1. Product Overview
1.1
INTRODUCTION
The KSZ8061MNX Evaluation Board is designed to enable functional and performance
testing of the KSZ8061MNX PHY. In addition to the KSZ8061 PHY, there is a second
PHY–a KSZ8081. The KSZ8081 is a standard 10/100 Ethernet PHY. It is used here to
provide a second line interface for simple full-duplex traffic through the KSZ8061. This
board is not intended for evaluation of the KSZ8081. A block diagram of the board is
shown in
.
highlights the board components.
FIGURE 1-1:
KSZ8061MNX EVALUATION BOARD BLOCK DIAGRAM
KSZ8061
Second PHY
(KSZ8081)
RJ-45
Line
Connector
(3 options)
MII Connector
10-Pin
Management
Header (J7)
R1-6
R21-26
R11-16
R2
21
-226
R2
11
-21
6
DC Power
Connector
Tx
Rx
MII
MII
Rx
Tx
Interrupt
Reset
MDIO/MDC
Signal Detect
Ma
gn
eti
c
s
Ma
gn
eti
c
s
KSZ8061 3.3V Reg
Sele
ct
KSZ8081 3.3V Reg
KSZ8061 Low V Reg
5V
En
RXER Latch,
LED, Reset
Reset
Reset
25 MHz
Xtal
Clocking Options