Microchip Technology EVB-KSZ9563, User Manual

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EVB-KSZ9563 Evaluation Board User’s Guide
DS500027
26A-page
2
1

2018 Microchip T
echnolo
gy Inc.
FIGURE B-1: EVB-KSZ9563 SCHEMATICS - KSZ9563 DEVICE, PIN STRAPPING, CLOCK, AND RESET
AVDDH
TXRX1B_P
TXRX1B_N
TXRX1C_P
TXRX1C_N
TXRX1D_P
TXRX1D_N
TXRX2A_P
TXRX2A_N
TXRX2B_P
TXRX2B_N
TXRX2C_P
TXRX2C_N
AVDDL
TX
R
X
2
D
_
P
TX
R
X
2
D
_
N
TXRX1B_P 3
TXRX1B_N 3
TXRX1C_P 3
TXRX1C_N 3
TXRX1D_P 3
TXRX1D_N 3
TXRX2A_P 3
TXRX2A_N 3
TXRX2B_P 3
TXRX2B_N 3
TXRX2C_P 3
TXRX2C_N 3
TXRX2D_P
TXRX2D_N
TXRX2D_P 3
TXRX2D_N 3
TXRX1A_P
TXRX1A_N
TXRX1A_P 3
TXRX1A_N 3
VDDIO
DVDDL
RX
D3_U1
RX
D2_U1
RX
D1_U1
RX
D0_U1
TX
D
3
TX
D
2
TX
D
1
TX
D
0
RX
_E
R_U1
RX
_DV
_
U1
RX
_CLK
_U1
SDI_SDA_MDIO
SDO
RESET_N
INTRP_N
PME_N
LED2_1
LED2_0
GPIO_2
GPIO_1
TX_ER
TX_EN
TX_CLK
SDI_SDA_MDIO 3
SDO 3
INTRP_N 3
PME_N 3
LED2_1 3
LED2_0 3
TX_ER 3
TX_EN 3
TX_CLK 3
TXD0 3
TXD1 3
TXD2 3
TXD3 3
RX_CLK 3
RXD0 3
RXD1 3
RXD2 3
RXD3 3
RX_ER 3
RX_DV 3
TXD0
TXD1
TXD2
TXD3
RXD0
RXD1
RXD2
RXD3
RX_DV
RX_CLK
RX_ER
SC
S
_
N
SC
L
_
MD
C
IS
E
T
TX
R
X
1
A
_
N
TX
R
X
1
A
_
P
XI XO LE
D1
_0
LE
D1
_1
SCL_MDC 3
SCS_N 3
SCL_MDC
SCS_N
LED1_1 3
LED1_0 3
LED1_1
LED1_0
6.04k
1%
R49
External Reference Clocks
Input clock
Output clock MMCX_SYNCLKO
MMCX_XI
For AVB/1588
Place close to KSZ9563RNX
Close for MMCX
Open for test point
Open always
0.1uF DNP
C17
15pF
DNP
C14
XO
15pF
DNP
C13
XTAL-MEMS_XI
VDDIO
0.1uF
C12
Place close
to pin 46
RST_N input stability option
GPIO_2
GPIO_1
INTRP_N
PME_N
"INTRP_N"
"PME_N"
Br Grn
D4
Br Grn
D5
VDDIO
470R
R20
470R
R43
4.7k
R51
4.7k
R50
VDDIO
Strapping Pins
Refer to KSZ9563RNX Datasheet for detailed descriptions.
Strapping pins have internal pull-ups/pull-downs (default values);
external pull-ups/pull-downs are used to override internal values.
1
1000Mbps 0
Port_3 Speed LED2_1
10/100Mbps (default)
0, 1
0, 0
1, 1
1, 0
RMII
MII (default)
Port_3 xMII Mode RXD3, RXD2
RGMII
<reserved>
MII: PHY Mode
1
RMII: Clock Mode - RMII 50MHz
Reference Clock output on RX_CLK pin
0
Port_3 MII / RMII Configuration LED2_0
(default)
MII: MAC Mode
RMII: Normal Mode - RMII 50MHz
Reference Clock input to TX_CLK pin
1
Start Switch disabled
Switch will not forward packets until the Start bit is set in Register 0x0_3_00. 0
Start Switch Configuration LED1_0
Start Switch enabled (default)
Switch will forward packets immediately after reset.
Auto-Negotiation enable with EEE enable (default)
PHY Ports 1 and 2 Configuration RX_ER, PME_N
0, 0
0, 1
1, 1
1, 0
<reserved>
Auto-Negotiation disable (Force 100Mbps, Full-duplex mode), and
Auto-MDIX disable (set to MDI-X mode)
Auto-Negotiation disable (Force 100Mbps, Full-duplex mode), and
Auto-MDIX disable (set to MDI mode)
VDDIO
RESET_N
0R
DNP
R18
0R
R19
0R
DNP
R48
0R
DNP
R47
25REFCLK_QTS
25REFCLK_QTS 3
from Samtec connector
22R R26
22R
R32
22R
R25
RX_DV_U1
RX_CLK_U1
RX_ER_U1
22R
R21
22R R22
22R R23
22R R24
RXD3_U1
RXD2_U1
RXD1_U1
RXD0_U1
RX_DV_U1
RX_CLK_U1
RX_ER_U1
RXD3_U1
RXD2_U1
RXD1_U1
RXD0_U1
i Net Class
ClassName: RGMII-RX_U1
100k
R12
VDDIO
MMBD914
D3
1uF
C8
1
4 2
3
SW1
Reset
0R
DNP
R13
0R
R11
RESET_N_QTS 3
RESET_N
from Samtec connector
RESET_N_QTS
RXD3_U1
RXD2_U1
RXD1_U1
RXD0_U1
RX_ER_U1
SDO_PU
4.7k
R29
4.7k
R36
4.7k R39
4.7k R42
4.7k DNP
R34
4.7k
R17
LED1_0
4.7k DNP
R2
LED1_1_PU
LED2_0
LED2_1
PME_N
4.7k
R7
4.7k DNP R35
4.7k DNP
R27
4.7k DNP
R52
RXD3_U1
RXD2_U1
RXD1_U1
RXD0_U1
RX_ER_U1
SDO_PD
RX_DV_U1
LED1_0
LED1_1_PD
LED2_0
LED2_1
PME_N
750R DNP
R3
750R
R10
750R R33
750R R28
750R DNP
R38
750R R44
750R DNP R30
750R DNP
R31
750R DNP
R40
750R DNP R41
750R
R37
750R
R16
1, x
0, 1
0, 0
Management Mode RXD1, RXD0
I2C Slave
MDC/MDIO (default)
SPI Slave
1
0
IBA Mode LED1_1
Disable
Enable (default)
1
0
Quiet-WIRE SDO
Enable
Disable (default)
0R
DNP
R14
0R R15
TP14
TP16
*2-3
Quiet-WIRE
1
2
3
J1
LED1_1_PD
LED1_1_PU
LED1_1
1
2
3
J5
SDO_PD
SDO_PU
SDO
*2-3
IBA Mode
GPIO_2
GPIO_1
XI
SYNCLKO
SYNCLKO
GND
Test Options
TXRX1P_B
1
TXRX1M_B
2
TXRX1P_C
3
TXRX1M_C
4
TXRX1P_D
6
AVDDL
5
TXRX1M_D
7
AVDDH
8
TXRX2P_A
9
TXRX2M_A
10
AVDDL
11
TXRX2P_B
12
TXRX2M_B
13
TXRX2P_C
14
TXRX2M_C
15
AVDDL
16
TXRX2
P_D
17
TXRX2
M_D
18
AV
D
D
H
19
DVDD
L
20
RXD3
21
RXD2
22
RXD1
23
RXD0
24
RXC
/
REFCLKO
/
R
X_CLK
25
VDDIO
26
RX_DV
/
CRS_DV
/
RX_CTL
27
RX_ER
28
TXD3
29
TXD2
30
TXD1
31
TXD0
32
TXC / REFCLKI / GTX_CLK
33
DVDDL
34
TX_EN / TX_CTL
35
TX_ER
36
DVDDL
37
VDDIO
38
GPIO_1
39
GPIO_2
40
DVDDL
41
LED2_0
42
LED2_1
43
PME_N
44
INTR_N
45
RST_N
46
SDO
47
SDI / SDA / MDIO
48
SC
S
_N
49
KSZ9563RNX
Paddle Ground (Chip Bottom)
(QFN64)
SCL
/
M
DC
50
P_
G
N
D
65
AV
D
D
H
61
TXRX
1P_A
62
TXRX
1M_A
63
AV
D
D
L
64
DV
D
D
L
51
L
ED1_0
52
L
ED1_1
53
V
D
DIO
54
DV
D
D
L
55
AV
D
D
L
56
XO
57
XI
58
GND
59
ISET
60
U1
Rosc
Rxtal
Rxo
P/N = ABM8G-25.000MHZ-B4Y-T (Murata)
P/N = DSC1001CI2-25.0000 (Microchip)
For Y1 = XTAL:
Populate Rxtal and Rxo
DNP Rosc
For Y1 = OSC (default):
Populate Rosc
DNP Rxtal and Rxo
DNP
1
MMCX, Vert
J4
DNP
1
MMCX, Vert
J3
JP2
JP1
TX_ER
TX_EN
TX_CLK
TXD0
TXD1
TXD2
TXD3
i Net Class
ClassName: RGMII-TX_U1
4.7k
DNP
R53
VDDIO
VDD
4
GND
2
STBY#
1
OUT
3
Y1