D
EBU
G
G
E
R
U
S
B M
IC
R
O
-B
C
O
N
N
E
C
T
O
R
GND
USBD_P
USBD_N
C107
C108
RX
TX
UART
CDC_UART
1k
R107
V
CC_P3V
3
SR
ST
ST
A
T
US_
LED
SH
IE
L
D
VB
U
S
V
CC_P3V
3
GND
TP
10
0
Te
st
po
in
t A
rr
ay
1
2
3
4
5
6
7
8
9
10
TC
K
TD
O
TM
S
Vsu
p
T
D
I
GND
TR
ST
SR
ST
V
T
ref
GND
J102
GND
4.
7u
F
C100
DBG0
DBG0
2
1
GREEN LED
SML-P12MT
T
86R
D100
VBUS
1
D-
2
D+
3
GND
5
SHIELD1
6
SHIELD2
7
ID
4
SHIELD3
8
SHIELD4
9
M
U
-M
B014
2A
B2-
269
J105
J105
PAD
33
PAD
PA00
1
PA01
2
PA02
3
PA03
4
GND
10
VDDAN
A
9
PA04
5
PA05
6
PA06
7
PA07
8
PA08
11
PA09
12
PA10
13
PA11
14
PA14
15
PA15
16
PA16
17
PA17
18
PA18
19
PA19
20
PA22
21
USB_SOF/PA23
22
USB_DM/PA24
23
USB_DP/PA25
24
PA27
25
RESET
N
26
PA28
27
GND
28
VDDCO
RE
29
VDDIN
30
SWDCL
K/P
A30
31
SWDIO
/PA3
1
32
SAMD
21
E
18
A-MUT
U100
VOUT
1
VOUT
2
GND
3
EN
4
VIN
6
NC
5
EP
7
M
IC552
8-3
.3YMT
U101
V
CC_P3V
3
GND
USBD_P
USBD_N
GND
C106
V
CC_MC
U
_C
O
R
E
V
CC_P3V
3
V
CC_P3V
3
G
ND
4.7
uF
C
10
0
VOUT
1
VOUT
2
GN
D
3
EN
4
VIN
6
N
C
5
EP
7
M
IC
55
28
-3
.3
Y
M
T
U
10
1
V
C
C_
P3
V
3
G
N
D
2.
2u
F
C101
GND
74
LVC1T
45FW4-7
VCCA
1
VCCB
6
A
3
GND
2
DIR
5
B
4
U103
V
CC_P3V
3
GND
74
LVC1T
45FW4-7
VCCA
1
VCCB
6
A
3
GND
2
DIR
5
B
4
U104
V
CC_P3V
3
GND
74
LVC1T
45FW4-7
VCCA
1
VCCB
6
A
3
GND
2
DIR
5
B
4
U105
V
CC_P3V
3
GND
GND
GND
GND
GND
74
LVC1T
45FW4-7
VCCA
1
VCCB
6
A
3
GND
2
DIR
5
B
4
U107
V
CC_P3V
3
GND
DBG2
DBG3_CTRL
S1
_0
_TX
S1
_1
_RX
S0
_2
_TX
DAC
VT
G
_AD
C
RESE
R
V
ED
S0
_3
_CLK
DBG0_C
TRL
CDC_T
X
_CTRL
BOOT
D
EBU
G
G
E
R
PO
W
E
R
/S
T
A
T
U
S L
E
D
1k
R
10
7
V
C
C_
P3
V
3
2
1
G
REEN
LE
D
SM
L-
P1
2M
T
T
86
R
D
10
0
EN
1
BYP
6
VOUT
4
GND
2
VIN
3
NC/ADJ
5
GND
7
M
IC5353
U102
C102
GND
GND
47k
R101
27k
R104
GND
33
k
R106
G
ND
EN
1
BYP
6
VOUT
4
G
N
D
2
VIN
3
NC
/
AD
J
5
G
N
D
7
M
IC
53
53
U
10
2
C
10
2
G
N
D
G
N
D
47k
47k
R10
1
27k
27k
R10
4
G
N
D
33
k
R
10
6
2.2uF
C103
GND
1k1k
R108
J100
V
CC_LEVE
L
V
CC_REGULAT
OR
74
LVC1T
45FW4-7
VCCA
1
VCCB
6
A
3
GND
2
DIR
5
B
4
U106
V
CC_P3V
3
GND
DBG1
CDC_RX
CDC_T
X
DBG3
DBG1_C
TRL
D
E
B
U
G
G
ER REGU
LATOR
REG_ENABLE
REG_ENABLE
47k
47k
47k
R103
V
CC_LEVE
L
V
CC_LEVE
L
V
CC_LEVE
L
V
CC_LEVE
L
V
CC_LEVE
L
47k
47k
47k
R102
47k
47k
47k
R105
SW
C
L
K
GND
47k
47k
47k
R100
GND
DBG2
S0
_0
_RX
DBG1_CTRL
DBG0_CTRL
G
ND
DB
G3
O
P
E
N
D
R
AI
N
TAR
G
ET AD
JUSTAB
LE REGULATOR
SRS
T
V
C
C_P
3V
3
G
N
D
T
es
tp
oin
t At
rrrr
ay
1
2
3
4
5
6
7
8
9
1
0
T
C
K
T
D
O
T
M
S
V
su
pu
T
DI
G
ND
T
RS
T
SRS
T
V
T
re
f
G
ND
J1
02
SW
C
LK
D
E
B
U
G
G
ER TESTPOINT
DBG2_C
TRL
VO
FF
CDC_RX_C
T
R
L
47k
47k
47k
R109
DBG1
CDC_T
X
_CTRL
CDC_RX_C
T
R
L
SW
C
L
K
REG_ADJ
UST
DBG2_G
PIO
DBG3_CTRL
DBG2_CTRL
Signal
DB
G
0
DB
G
1
DB
G
2
DB
G
3
SW
D
In
te
rf
ac
e
SW
DAT
SW
C
L
K
GPIO
nR
ESE
T
DBG3
C
DC TX
C
DC RX
U
A
R
T
RX
UART TX
T
ARG
E
T
1k1k
R110
VBUS_ADC
1
2
3
DMN65D8LFB
Q101
VC
C
3.3V
ID_SYS
VOFF
1k
R112
V
CC_P3V
3
I
D
_S
Y
S
1k
1k
R11
2
V
C
C_
P3
V
3
VT
G
_AD
C
DAC
M
IC94163
VIN
B2
VOUT
A1
VIN
A2
EN
C2
GND
C1
VOUT
B1
U108
U108
GND
ID
_S
Y
S
VT
G
_E
N
VTG_EN
VBUS_ADC
SW
DIO
ID
_S
Y
S
TP
10
1
GND
SW
DIO
VO
FF
47k
47k
47k
R111
GND
ID PIN
M
C
3621
3
F1
00
V
CC_VB
U
S
V
CC_VB
U
S
V
CC_VB
U
S
V
CC_EDGE
J101
V
CC_TA
RGET
10k
R113
GND
BLM15PD80
0SN1
L100
SR
ST
10
0n
F
10
0n
F
1u
F
10
0n
F
A
V
R program
m
in
g
connect
or for factor
y
prog
ram
m
ing
of
DEBUGGER.
M
IC552
8:
V
in
: 2.5
V
to 5.5
V
V
ou
t: Fi
xed
3.3V
Imax
: 5
00mA
Drop
out
: 260
m
V
@
500m
A
M
IC5353:
Vin:
2
.6V t
o 6V
V
ou
t: 1.25
V
to
5.1V
Imax
: 5
00mA
Drop
out
(t
yp
ica
l):
50
m
V
@
150m
A
, 16
0m
V
@ 500
m
A
A
ccurac
y:
2%
initi
al
T
her
m
al shutdown and current li
m
it
M
ax
im
um
outp
ut
volt
age
is lim
ite
d by
the in
put
v
ol
tag
e and
the dr
opo
ut
vo
ltage
in the
regu
lat
or.
(V
m
ax
= Vi
n - drop
out
)
A
dj
ust
abl
e out
put
and li
m
itat
ion
s:
- T
he
DEBUGGER can
adju
st
th
e out
put
v
ol
tag
e of th
e reg
ula
tor
between
1.25
V
and 5.1V
to th
e tar
get
.
- Th
e le
vel sh
ift
ers
ha
ve
a m
inim
al
v
ol
tag
e lev
el
of 1.65V
and
will
li
m
it th
e m
inim
um
ope
rat
ing
v
ol
tag
e all
owed for
the
target to stil
l all
ow co
m
m
un
ica
tio
n.
- Th
e outp
ut switc
h has
a mi
ni
m
al
vo
la
teg
e lev
el
of 1.70V
and
will
li
m
it th
e m
inim
um
v
ol
ta
ge de
liv
er
ed to
the ta
rge
t.
- F
ir
m
w
ar
e c
on
fi
gu
ra
tio
n w
ill
li
mit
th
e v
olt
ag
e r
ang
e t
o b
e w
ith
in
th
e t
he
ta
rg
et s
pe
ci
fic
at
io
n.
- Firm
ware fe
edb
ack
loop
will
adju
st th
e out
put
v
ol
tag
e acc
ura
cy
to
with
in 0.5
%
.
PT
C Rese
tta
ble
fuse
:
Hold curr
ent
: 500m
A
T
ri
p cur
ren
t: 10
00m
A
J100:
Cut-
str
ap us
ed for ful
l separation of target power
fr
om
the le
ve
l shi
fte
rs an
d on-
boa
rd re
gul
ato
rs.
- For cu
rre
nt
m
eas
ure
m
ents
usin
g an ex
ter
nal
power sup
ply
, th
is st
rap
coul
d be cu
t for
mo
re
accurat
e m
easurem
ents. Leakage
back thr
ough the swit
ch is
in the mi
cro am
pere range.
J101:
T
hi
s is fo
otp
rin
t for
a 1x2 10
0m
il pi
tch
pin-
hea
der
that
can be
used
for ea
sy
cu
rre
nt
m
eas
ure
m
en
t
to
the
targ
et
m
icr
oco
ntr
oll
er an
d the
LED / But
to
n.
To
us
e the
foot
pri
nt:
- Cut th
e tra
ck be
tween th
e hol
es, and
mo
un
t a pi
n-h
ead
er
EV76S68A
Schematics
©
2020 Microchip Technology Inc.
User Guide
DS70005432A-page 18
