Microchip Technology dsPIC30F6010, Datasheet

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2004 Microchip Technology Inc.
Advance Information
DS70119B-page 75
dsPIC30F6010
13.0 OUTPUT COMPARE MODULE
This section describes the Output Compare module
and associated operational modes. The features pro-
vided by this module are useful in applications requiring
operational modes such as:
• Generation of Variable Width Output Pulses
• Power Factor Correction
Figure 13-1 depicts a block diagram of the Output
Compare module.
The key operational features of the Output Compare
module include:
• Timer2 and Timer3 Selection mode
• Simple Output Compare Match mode
• Dual Output Compare Match mode
• Simple PWM mode
• Output Compare during Sleep and Idle modes
• Interrupt on Output Compare/PWM Event
These operating modes are determined by setting the
appropriate bits in the 16-bit OCxCON SFR (where x =
1,2,3,...,N). The dsPIC30F6010 device has 8 compare
channels.
OCxRS and OCxR in the figure represent the Dual
Compare registers. In the dual compare mode, the
OCxR register is used for the first compare and OCxRS
is used for the second compare.
FIGURE 13-1: OUTPUT COMPARE MODE BLOCK DIAGRAM
OCxR
Comparator
Output
Logic
Q S
R
OCM<2:0>
Output Enable
OCx
Set Flag bit
OCxIF
OCxRS
Mode Select
3
Note:
Where ‘x’ is shown, reference is made to the registers associated with the respective output compare
channels 1 through N.
OCFA
OCTSEL
0
1
T2P2_MATCH TMR2<15:0 TMR3<15:0>
T3P3_MATCH
From GP Timer Module
(for x = 1, 2, 3 or 4)
or OCFB
(for x = 5, 6, 7 or 8)
0
1