1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
D
D
C
C
B
B
A
A
3
of
4
A
Tt
in
y3
21
7
C
ur
io
si
ty
N
an
o
27
/1
1/2019
A
Tt
in
y3
21
7_
C
uri
os
it
y_
N
an
o_
D
ebu
gg
er
.S
ch
D
oc
Pr
oj
ec
t T
itle
PC
B
Asse
mbly
Numbe
r:
PC
B
A
Re
vis
ion:
File:
PCB
Numb
er:
PC
B
Re
vi
si
on
:
D
es
ig
ne
d
w
ith
Dra
wn
By
:
M.LOPER
Sh
ee
t T
itle
Deb
ug
ger
Engineer:
PB
/
TF
A08-3055
2
Size
A
3
A09-3333
2
Page:
Date:
Alt
ium
.co
m
GND
USBD_P
USBD_N
100n
C107
100n
C108
RX
TX
U
A
R
T
CD
C_
UA
RT
1k
R107
VCC_P3V3
SRST
ST
A
TUS_LED
SHIELD
VCC_P3V3
GND
TP100
Te
st
po
in
t Array
1
2
3
4
5
6
7
8
9
10
TCK
TDO
TMS
Vsup
TDI
GND
TRST
SRST
V
T
ref
GND
J102
GND
4.
7u
F
C100
DB
G0
DBG0
2
1
GRE
EN
LED
SML-P12MTT86R
D100
VB
US
1
D-
2
D+
3
GN
D
5
SH
IE
LD
1
6
SH
IE
LD
2
7
ID
4
SH
IE
LD
3
8
SH
IE
LD
4
9
MU-MB0142AB2-269
J105
PA
D
33
PA
00
1
PA
01
2
PA
02
3
PA
03
4
G ND
10
VDD
ANA
9
PA
04
5
PA
05
6
PA
06
7
PA
07
8
PA08
11
PA09
12
PA10
13
PA11
14
PA14
15
PA15
16
PA
16
17
PA
17
18
PA
18
19
PA
19
20
PA
22
21
US
B_
SO
F/
PA
23
22
US
B_
DM
/PA
24
23
US
B_
DP/
PA
25
24
PA27
25
RES
ETN
26
PA28
27
G ND
28
VDD
COR
E
29
VDD
IN
30
SWD
CLK
/PA
30
31
SWD
IO
/PA
31
32
SAMD21E18A-MUT
U100
VO
UT
1
VO
UT
2
G ND
3
EN
4
VI
N
6
NC
5
EP
7
MIC5
528-3
.3YM
T
U101
VCC_VBUS
VCC_P3V3
GND
USBD_P
USBD_N
GND
1u
C106
VCC_MCU_CORE
VCC_P3V3
VCC_P3V3
2.
2u
F
C101
GND
74
L
VC1T45FW4-7
VC
CA
1
VC
CB
6
A
3
GN
D
2
DI
R
5
B
4
U103
VCC_P3V3
GND
74
L
VC1T45FW4-7
VC
CA
1
VC
CB
6
A
3
GN
D
2
DI
R
5
B
4
U104
VCC_P3V3
GND
74
L
VC1T45FW4-7
VC
CA
1
VC
CB
6
A
3
GN
D
2
DI
R
5
B
4
U105
VCC_P3V3
GND
GND
GND
GND
GND
74
L
VC1T45FW4-7
VC
CA
1
VC
CB
6
A
3
GN
D
2
DI
R
5
B
4
U107
VCC_P3V3
GND
DB
G2
DBG3_CTRL
S1_0_TX
S1_1_RX
S0_2_TX
DAC
VTG_ADC
R
E
SE
R
VED
S0_3_CLK
DBG0_CTRL
CDC_TX_CTRL
BOOT
D
E
B
U
GG
E
R
P
O
W
E
R
/S
T
A
T
U
S
L
E
D
EN
1
BY
P
6
VO
UT
4
GN
D
2
VI
N
3
NC
/A
DJ
5
GN
D
7
MIC5353
U102
VCC_VBUS
100n
C102
GND
GND
47k
R101
27k
R104
GND
33k
R106
2.
2u
F
C103
GND
1k
R108
J100
VCC_LEVEL
V
C
C
_R
E
G
U
L
A
T
OR
74
L
VC1T45FW4-7
VC
CA
1
VC
CB
6
A
3
GN
D
2
DI
R
5
B
4
U106
VCC_P3V3
GND
DB
G1
CDC_RX
CDC_TX
DB
G3
DBG1_CTRL
D
E
B
U
G
G
E
R
R
E
G
U
L
A
T
O
R
REG_ENABLE
REG_ENABLE
47k
R103
VCC_LEVEL
VCC_LEVEL
VCC_LEVEL
VCC_LEVEL
VCC_LEVEL
47k
R102
47k
R105
SWCLK
GND
47k
R100
GND
DBG2
S0_0_RX
DBG1_CTRL
DBG0_CTRL
D
B
G
3
O
P
E
N
D
R
A
IN
TA
R
GE
T
A
D
JU
ST
A
B
L
E
R
E
G
U
L
A
T
O
R
SRST
D
E
B
U
GGE
R
T
E
ST
PO
IN
T
s
DBG2_CTRL
VOFF
CDC_RX_CTRL
47k
R109
DBG1
CDC_TX_CTRL
CDC_RX_CTRL
SWCLK
REG_ADJUST
DBG2_GPIO
DBG3_CTRL
DBG2_CTRL
U
P
D
I
UPDI
GPIO
GPIO
RESET
Si
gn
al
D
B
G0
D
B
G1
D
B
G2
D
B
G3
IC
SP
In
te
rf
ac
e
D
A
T
CLK
GPIO
MCLR
DBG3
C
D
C
T
X
C
D
C
R
X
U
A
R
T
R
X
U
A
R
T
T
X
U
A
R
T
R
X
U
A
R
T
T
X
TA
R
G
E
T
TA
R
GE
T
1k
R
110
VBUS_ADC
DMN65D8LFB
1
2
3
Q101
V
C
C
-
-
ID
_S
YS
VO
FF
1k
R112
VCC_P3V3
VTG_ADC
DAC
MIC94163
VI
N
B2
VO
UT
A1
VI
N
A2
EN
C2
GN
D
C1
VO
UT
B1
U108
GND
ID_SYS
VTG_EN
VTG_EN
VBUS_ADC
SWDIO
ID_SYS
TP101
GND
SWDIO
VOFF
47k
R111
GND
ID
P
IN
D
E
B
U
GG
E
R
U
SB
M
IC
R
O
-B
C
O
N
N
E
C
T
O
R
VBUS
MC36213
F100
VCC_VBUS
VCC_EDGE
J101
V
C
C
_T
ARGET
47k
R
113
Pro
gram
mi
ng c
onn
ect
or
fo
r
fa
ct
or
y
pr
og
ra
mm
in
g
of
Debugger
MIC5528:
V
in: 2.5V
to
5
.5
V
V
ou
t:
F
ix
ed
3
.3
V
Ima
x:
500
mA
Drop
out:
260m
V
@
5
00
m
A
Adju
sta
ble
out
put
and
li
mita
tio
ns:
- T
he
DEB
UGG
ER
ca
n a
dj
ust
th
e
out
put
v
olt
age
of
the
reg
ul
at
or
be
twe
en
1.
25V
and
5.
1V
to
the
ta
rg
et
.
-
Th
e
vo
lt
ag
e
out
pu
t is
li
mi
te
d
by
the
inp
ut
(U
SB)
, w
hi
ch
c
an
va
ry
be
tw
ee
n
4.4
0V
to
5
.2
5V
- T
he
lev
el
sh
ift
ers
ha
ve
a m
ini
ma
l vol
tag
e
le
vel
of
1
.65
V a
nd
w
il
l li
mi
t th
e
mi
ni
mu
m
op
er
at
in
g
vo
lt
ag
e
al
lo
we
d
fo
r
th
e
ta
rge
t to
s
ti
ll
a
ll
ow
c
om
mu
ni
ca
ti
on
.
- T
he
MI
C94
163
ha
s a
m
ini
ma
l v
ol
ate
ge
le
ve
l o
f 1
.70
V
an
d w
il
l l
im
it
th
e m
in
im
um
vol
ta
ge
de
liv
ere
d
to
the
tar
ge
t.
-
Fir
mwa
re
con
fig
ura
ti
on
wil
l l
im
it
the
vol
ta
ge
ran
ge
to
be
wi
th
in
the
th
e t
ar
ge
t s
pec
if
ica
tio
n.
PTC
Re
sett
abl
e fu
se:
Hol
d c
urr
ent
: 500
mA
T
rip
c
urr
ent
: 1
000
mA
MIC5353:
V
in: 2.6V
to
6
V
V
out: 1.25V
to
5
.1
V
Ima
x:
500
mA
Drop
out
(typ
ical
): 5
0mV@
150m
A, 16
0mV
@
5
00
m
A
Acc
ura
cy:
2%
in
iti
al
The
rma
l shu
tdo
wn
an
d c
urr
en
t l
im
it
Max
imu
m o
utpu
t v
olt
age
is
li
mit
ed
by
the
in
put
vol
tag
e a
nd
the
dr
opou
t v
olt
age
in
th
e r
egu
lat
or.
(V
m
ax
=
V
in
-
d
ro
po
ut
)
J100:
Cut
-st
rap
us
ed
for
fu
ll
se
par
ati
on
of
ta
rge
t po
we
r
fr
om
the
lev
el
s
hi
ft
er
s
an
d
on
-b
oa
rd
re
gu
la
to
rs.
- For c
urrent
measur
ements
using a
n exte
rnal po
wer supp
ly,
thi
s
str
ap
co
ul
d
be
c
ut
fo
r
m
or
e
ac
cu
ra
te
m
ea
su
re
me
nt
s.
L
ea
ka
ge
b
ac
k
th
ro
ug
h
th
e
sw
it
ch
is
in
the
m
ic
ro
a
mp
er
e
ra
ng
e.
J101:
Th
is
is
fo
ot
pr
in
t fo
r
a
1x
2
10
0m
il
p
it
ch
p
in
-h
ea
de
r
th
at
c
an
b
e
us
ed
f
or
e
as
y
cu
rr
en
t me
as
ur
em
en
t
to the target microcont
roller an
d the LED
/ Button
. To u
se
th
e
foo
tp
ri
nt
:
-
Cu
t th
e
tra
ck
b
et
we
en
the
h
ol
es
, an
d
mo
un
t a
pi
n-
he
ad
er
R
113
is
re
qu
ir
ed
to
p
ul
l th
e
Q1
01
g
ate
to
a
de
fin
ed
va
lue
w
he
n
th
e
U1
00
is
no
t
powered
ATtiny3217
Appendix
©
2020 Microchip Technology Inc.
User Guide
DS40002193A-page 31
