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Microchip Technology ATSAMR30M18A Datasheet Download Page 47

Figure 12-5. Layer 2 (GND) Layout

The following figure shows the bottom layer layout of the reference board directly beneath the RF traces.

Figure 12-6. Bottom Layer Layout

The following image shows the PCB stack-up for the reference board. Layer 1 (Top Layer) and Layer 2 specifications
are critical to the RF Trace Layout specification.

 ATSAMR30M18A

Application Reference Design

©

 2018-2021 Microchip Technology Inc.

and its subsidiaries

 Datasheet

DS70005384B-page 47

Summary of Contents for ATSAMR30M18A

Page 1: ...er Micro Trace Buffer MTB Memories 256 KB in system self programmable Flash 32 KB SRAM 8 KB low power RAM System Power on Reset POR and Brown out Detection BOD Internal clock option with 48 MHz Digital Frequency Locked Loop DFLL48M and 48 MHz to 96 MHz Fractional Digital Phase Locked Loop FDPLL96M External Interrupt Controller EIC Up to 14 external interrupts One non maskable interrupt Two pin Ser...

Page 2: ... width modulation PWM pattern across port pins Deterministic fault protection fast decay and configurable dead time between complementary output Dithering that increase resolution with up to 5 bit and reduce quantization error 32 bit Real Time Counter RTC with clock calendar function Watchdog Timer WDT CRC 32 generator One full speed 12 Mbps Universal Serial Bus USB 2 0 interface Embedded host and...

Page 3: ...igital Phased Locked Loop FDPLL96M I O and Package 16 programmable I O pins 25 pin module package 12 7 mm x 11 0 mm with castellated PCB pads Operating Voltage 1 8V 3 6V Temperature Range 40 C to 85 C Industrial Power Consumption 1 RX_ON 10 79 mA BUSY_TX 26 97 mA Standby 2 03 µA Backup mode 0 77 µA Note 1 For more details see 9 3 4 Current Consumption Specifications ATSAMR30M18A 2018 2021 Microchi...

Page 4: ...Frequency Synthesizer PLL 26 7 7 Automatic Filter Tuning FTN 29 8 Radio Transceiver Usage 31 8 1 Frame Receive Procedure 31 8 2 Frame Transmit Procedure 31 9 Electrical Characteristics 33 9 1 Absolute Maximum Ratings 33 9 2 Recommended Operating Conditions 33 9 3 Module Performance 33 10 Mechanical Description 41 10 1 Module Outline Drawings 41 10 2 Footprint 42 11 Design Considerations 43 11 1 Ap...

Page 5: ...2 16 Document Revision History 63 The Microchip Website 64 Product Change Notification Service 64 Customer Support 64 Microchip Devices Code Protection Feature 64 Legal Notice 65 Trademarks 65 Quality Management System 66 Worldwide Sales and Service 67 ATSAMR30M18A 2018 2021 Microchip Technology Inc and its subsidiaries Datasheet DS70005384B page 5 ...

Page 6: ... I RMxxx SAM R30 Module in Tape and Reel package Figure 1 1 Module Ordering Code Information ATSAMR 30 M 18 A T I RM xxx Product Family SAMR Microcontroller with RF Product Series 30 Cortex M0 CPU Sub GHz 802 15 4 Transceiver Pin Count M Module Flash Memory Density 18 256 KB Device Variant A Hardware Revision xxx Bootloader FW Version Package Type RM Radio Module Temperature Rating I 40 to 85C Pac...

Page 7: ...nsions Table 2 1 ATSAMR30M18A Package Information Parameter Value Units Package size 12 7 x 11 0 mm Pad count 25 Total thickness 2 71 mm Pad pitch 1 2 mm Pad width 0 8 mm ATSAMR30M18A Package Information 2018 2021 Microchip Technology Inc and its subsidiaries Datasheet DS70005384B page 7 ...

Page 8: ...icon dies SAM L21 ARM Cortex M0 based microcontroller AT86RF212B low power low voltage 700 800 900 MHz transceiver The local communication and control interface is wired within the package Key I O external signals are exposed as I O pins 3 1 Interconnection between SAM L21 and AT86RF212B within ATSAMR30E18A SiP This section describes the interconnection between SAM L21 and AT86RF212B The interface...

Page 9: ... function is configured by hardware automatically after reset EXTINT1 The SPI is used for register Frame Buffer SRAM and AES access The additional control signals are connected to the GPIO IRQ interface of the microcontroller The following table introduces the radio transceiver I O signals and their functionality Table 3 1 Microcontroller Interface Signal Description Signal Description SEL SPI sel...

Page 10: ... a complete radio transceiver interface between radio frequency signals and the baseband microcontroller It comprises a bidirectional analog RF front end direct conversion mixers low noise fractional n PLL quadrature digitizer DSP modem and baseband packet handler optimized for IEEE 802 15 4 MAC PHY automation and low power An SPI accessible 128 byte TRX buffer stores receive or transmit data Radi...

Page 11: ...mpliant networks the radio transceiver supports proprietary High Data Rate Modes based on O QPSK Additionally the AT86RF212B provides BPSK 40 ALT wideband BPSK mode for compliance with FCC rule 15 247 and backward compatibility with legacy BPSK networks The AT86RF212B features hardware supported 128 bit security operation The standalone AES encryption decryption engine can be accessed in parallel ...

Page 12: ...D ATSAMR30E18A The module pin assignment is shown in the following table The SiP pin column is a reference to the ATSAMR30E18 datasheet ATSAMR30E18A Table 4 1 ATSAMR30M18A Module Pin Assignment Module SAMR30E Pin No Pin Name Possible Peripheral Function 1 SiP Pin Pin Description J1 PA24 UART5_Tx 22 EXTINT 12 SERCOM3 or 5 PAD 2 TC1 WO 0 TCC1 WO 2 USB DM CCL2 IN 2 J2 PA25 UART5_Rx 23 EXTINT 13 SERCO...

Page 13: ...1 or 3 PAD 1 TCC2 WO 1 TCC0 WO 7 GCLK IO 3 CCL0 IN 1 J8 PA18 SPI1_MOSI 19 EXTINT 2 PTC_X 6 SERCOM1 or 3 PAD 2 TC4 WO 0 TCC0 WO 2 AC CMP 0 CCL0 IN 2 J9 PA19 SPI1_SCK 20 EXTINT 3 PTC_X 7 SERCOM1 or 3 PAD 3 TC4 WO 1 TCC0 WO 3 AC CMP 1 CCL0 OUT J10 PA27 GPIO 25 EXTINT 15 GCLK IO 0 J11 PA28 GPIO 27 EXTINT 8 GCLK IO 0 J12 VDD 4 24 30 Power VDDANA VDDIO VDDIN J13 GND GND 3 6 11 14 28 Ground J14 RESET nRS...

Page 14: ...ERCOM0 or 2 PAD 1 TCC0 WO 1 TCC1 WO 3 CCL1 IN 1 J21 GND 3 6 11 14 28 Ground J22 GND 3 6 11 14 28 Ground J23 RF OUT RFP RFN 12 13 50 ohm single ended RF Output J24 GND 3 6 11 14 28 Ground J25 GND 3 6 11 14 28 Ground Notes 1 The peripheral function indicated in this column is based on the reference design This is one of the possibilities as each ATSAMR30E18A pin supports several multiplexed peripher...

Page 15: ...ta structure 2 bytes BOARD_SERIAL and PART_NO for this ATSAMR30M18A will be programmed with 0xFF The end user application software must copy two data fields to radio transceiver registers The data in MAC_IEEE_ADDRESS must be copied to the registers IEEE_ADDR_0 to IEEE_ADDR_7 of AT86RF212B The MAC_IEEE_ADDRESS is stored little endian with the first byte stored at the lowest address The XTAL_TRIM va...

Page 16: ...ser Row with the default value of 0x7 Customers not using the bootloader must program the BOOTPROT bits to default value to program the complete Flash of the SAMR30 device For detailed information refer to the boot loader manual The related information is available in the AVR2054 Application Note ATSAMR30M18A Boot Loader 2018 2021 Microchip Technology Inc and its subsidiaries Datasheet DS70005384B...

Page 17: ...ed by the AT86RF212B with a fixed chip rate of either 400 kchip s or 1000 kchip s At a chip rate of 400 kchip s there is a choice between two different Pulse Shaping modes One Pulse Shaping mode uses a combination of both half sine shaping SIN and raised cosine filtering with roll off factor 0 2 RC 0 2 according to IEEE 802 15 4 2006 2 for the 868 3 MHz band The other uses raised cosine filtering ...

Page 18: ...TRX_OFF state 7 1 4 Symbol Period Within IEEE 802 15 4 and accordingly within this document time references are often specified in units of symbol periods leading to a PHY mode independent description The table below shows the duration of the symbol period Table 7 2 Duration of the Symbol Period Modulation PSDU Data Rate kb s Duration of Symbol Period µs BPSK 20 50 40 25 O QPSK 100 200 400 40 250 ...

Page 19: ...hree symbol periods for 500 and 1000 kb s data rates The reduced acknowledgment time is untouched in IEEE 802 15 4 Otherwise it defaults to 12 symbol periods according to IEEE 802 15 4 Receiver Sensitivity Control The different data rates between PPDU header SHR and PHR and PHY payload PSDU cause a different sensitivity between header and payload This can be adjusted by defining sensitivity thresh...

Page 20: ...ve Procedure The frame receive procedure including the radio transceiver setup for reception and reading PSDU data from the Frame Buffer is described in the Frame Receive Procedure section 7 2 3 Configuration In Basic Operating Mode the receiver is enabled by writing command RX_ON to the TRX_CMD bits in the TRX_STATE register TRX_STATE TRX_CMD in states TRX_OFF or PLL_ON In Extended Operating Mode...

Page 21: ...ng on the transaction phase of either RX_AACK or TX_ARET 7 3 2 Frame Transmit Procedure The frame transmit procedure including writing PSDU data into the Frame Buffer and initiating a transmission is described in the Radio Transceiver Usage Frame Transmit Procedure section 7 3 3 TX Output Power The maximum output power of the transmitter is typically 3 2 dBm in normal mode and 8 7 dBm in boost mod...

Page 22: ...th American Band PHY Modes BPSK 40 GC_TX_OFFS 3 BPSK 40 ALT GC_TX_OFFS 3 OQPSK SIN 250 500 1000 GC_TX_OFFS 2 868 3 MHz European Band PHY Modes BPSK 20 GC_TX_OFFS 3 OQPSK SIN RC 100 200 400 GC_TX_OFFS 2 OQPSK RC 100 200 400 GC_TX_OFFS 3 780 MHz Chinese Band PHY Modes OQPSK RC 250 500 1000 GC_TX_OFFS 2 11 0xC0 0xA0 0xC1 10 0xC1 0x80 0xE3 9 0x80 0xE4 0xE4 8 0x82 0xE6 0xC5 7 0x83 0xE7 0xE7 6 0x84 0xE8...

Page 23: ...usly accessible The Frame Buffer utilizes the SRAM address space 0x00 to 0x7F for RX and TX operation of the radio transceiver and can keep a single IEEE 802 15 4 RX or a single TX frame of maximum length at a time Frame Buffer access conflicts are indicated by an underrun interrupt IRQ_6 TRX_UR Note The IRQ_6 TRX_UR interrupt also occurs on the attempt to write frames longer than 127 octets to th...

Page 24: ...t frame format as shown in the figure below Figure 7 4 AT86RF212B Frame Structure Preamble Sequence SFD PHR Payload LQI FCS 0 4 5 6 n 3 n 5 n 6 Frame Access Length octets Duration 4 octets 1 n octets n 128 3 octets Frame Buffer content TX Frame Buffer or SRAM write access RX SRAM read access ED RX_STATUS n 7 n 8 RX Frame Buffer read access SHR not accessible PHY generated A frame comprises two sec...

Page 25: ...upt occurs Nevertheless the old frame data can be read if the SPI data rate is higher than the effective PHY data rate A minimum SPI clock rate of 1MHz is recommended in this case Finally the microcontroller checks the integrity of the transferred frame data by calculating the FCS 3 When writing data to the Frame Buffer during frame transmission the SPI data rate shall be higher than the PHY data ...

Page 26: ...value needs to be loaded into the register during initialization For more details see NVM Information 7 5 3 Clock Jitter The ATSAMR30M18A provides receiver sensitivities up to 105 dBm Detection of such small RF signals requires very clean scenarios with respect to noise and interference Harmonics of digital signals may degrade the performance if they interfere with the wanted RF signal A small clo...

Page 27: ...L_1 register CC_CTRL_1 CC_BAND and CC_NUMBER bits in the CC_CTRL_0 register CC_CTRL_0 CC_CTRL_0 The table below shows the settings of CC_BAND and CC_NUMBER Table 7 4 Frequency Bands and Numbers CC_BAND CC_NUMBER Description 0 Not used European and North American channels according to IEEE 802 15 4 Frequency selected by the CHANNEL bits in the PHY_CC_CCA register PHY_CC_CCA CHANNEL 1 0x00 0xFF 769 ...

Page 28: ...ng state transition from TRX_OFF to PLL_ON or RX_ON state Additionally both calibration loops are initiated when the PLL changes to a different frequency setting If the PLL operates for a long time on the same channel for example more than five minutes or the operating temperature changes significantly it is recommended to initiate the calibration loops manually Both calibration loops can be initi...

Page 29: ...uccessful transmission does not generate an IRQ_0 PLL_LOCK within the settling period 7 7 Automatic Filter Tuning FTN The Automatic Filter Tuning FTN is incorporated to compensate device tolerances for temperature and supply voltage variations as well as part to part variations of the radio transceiver The filter tuning result is used to correct the analog baseband filter transfer function and the...

Page 30: ...inst Band Pass Filter BPF transfer function variations The recommended calibration interval is five minutes or less if the AT86RF212B operates always in an active state PLL_ON TX_ARET_ON RX_ON and RX_AACK_ON ATSAMR30M18A Module Description 2018 2021 Microchip Technology Inc and its subsidiaries Datasheet DS70005384B page 30 ...

Page 31: ...ller during Receive AT86RF212B Microcontroller IRQ issued IRQ_2 Read IRQ status pin 24 IRQ deasserted IRQ issued IRQ_3 Read frame data Frame Buffer access Read IRQ status pin 24 IRQ deasserted Critical protocol timing could require starting the Frame Buffer read access after interrupt IRQ_2 RX_START The first byte of the frame data can be read 32µs after the IRQ_2 RX_START interrupt The microcontr...

Page 32: ...st be higher than the PHY data rate to avoid a Frame Buffer underrun which is indicated by IRQ_6 TRX_UR Figure 8 3 Time Optimized Frame Transmit Procedure IRQ_3 TRX_END issued Write frame data Frame Buffer access Write TRX_CMD TX_START or assert pin 11 SLP_TR AT86RF212B Microcontroller Read IRQ_STATUS register pin 24 IRQ deasserted For more details about the internal interface lines like the SPI_C...

Page 33: ...AMR30 human body model 4 kV Charged device model 450 V PRF Input RF level 12 dBm Note 1 This value is derived from the ATSAMR30E18A IC 9 2 Recommended Operating Conditions The following table provides the recommended operating conditions for the ATSAMR30M18A module Table 9 2 Recommended Operating Conditions Symbol Parameter Min Typ Max Unit TOP Operating temperature range 40 25 85 C VDD Supply vol...

Page 34: ...20 kb s BPSK as specified in 1 2 40 kb s O QPSK as specified in 2 1 100 kb s O QPSK as specified in 2 3 2 250 kb s OQPSK_DATA_RATE 1 1 200 kb s OQPSK_DATA_RATE 2 1 400 kb s OQPSK_DATA_RATE 1 2 500 kb s OQPSK_DATA_RATE 2 2 1000 kb s fCLK Crystal oscillator frequency Reference oscillator 16 MHz fSRD Symbol rate deviation Reference frequency accuracy for correct functionality PSDU bit rate 20 40 100 ...

Page 35: ... 61 64 dBm 868 3 MHz 69 31 dBm PSPUR_TX Spurious Emissions 4 30 1000 MHz 54 38 dBm 1 12 75 GHz 46 72 dBm 1 Power settings according to the TX_PWR bits in the PHY_TX_PWR register PHY_TX_PWR TX_PWR 2 The EVM of OQPSK SIN RC 100 is significantly higher than the EVM of the other modulation schemes This phenomenon can be explained by the fact that the combination of SIN and RC shaping as specified in I...

Page 36: ... 4 34 3 0x05 3 9 0x49 5 44 4 0x07 5 9 0x29 6 65 5 0x08 7 0x90 7 43 6 0x91 8 22 0x91 8 48 7 0x09 8 11 0x93 10 12 8 0x0B 9 92 0x94 11 01 9 0x0C 10 91 0x2F 12 17 10 0x0D 11 96 0x30 13 14 11 0x0E 12 64 0x31 14 16 12 0x0F 13 73 0x0F 14 74 13 0x10 14 68 0x10 15 72 14 0x11 15 74 0x11 16 78 15 0x12 16 42 0x12 17 43 16 0x13 17 5 0x13 18 5 17 0x14 18 42 0x14 19 46 18 0x15 19 46 0x15 20 48 19 0x16 20 2 0x17 ...

Page 37: ...3 MHz BPSK 20 1 3 105 dBm OQPSK SIN RC 100 1 4 96 dBm OQPSK SIN RC 200 2 94 dBm OQPSK SIN RC 400 2 86 dBm OQPSK RC 100 1 97 dBm OQPSK RC 200 2 95 dBm OQPSK RC 400 2 92 dBm fRF 914 MHz BPSK 40 1 3 103 3 dBm OQPSK SIN 250 1 4 95 dBm OQPSK SIN 500 2 93 dBm OQPSK SIN 1000 2 88 dBm PRX_MAX Maximum RX input level 1 9 12 dBm PCRSB20 Channel rejection selectivity BPSK 20 3 fRF 868 3 MHz PRF 89 dBm 1 2 MHz...

Page 38: ... OQPSK RC 250 5 PRF 82 dBm 1 2 MHz 32 dB 2 MHz 32 dB PAACROR250 Alternate channel rejection OQPSK RC 250 5 PRF 82 dBm 1 4 MHz 50 dB 4 MHz 50 dB RXBL Blocking fRF 868 3 MHz Refer to ETSI EN 300 220 1 PRF 90 dBm 1 BPSK 20 2 MHz 38 dB BPSK 20 10 MHz 71 dB OQPSK SIN RC 100 2 MHz 34 dB OQPSK SIN RC 100 10 MHz 68 dB PSPUR_RX Spurious emissions LO leakage 74 dBm 30 1000 MHz 60 45 dBm 1 12 75 GHz 60 74 dB...

Page 39: ...ns except where noted Operating Conditions VDD 3 3V Temperature at 25 C CPU is running on Flash with one Wait state in PL0 and two Wait states in PL2 Low power cache is enabled BOD33 is disabled State of AT86RF212B is as specified in the following table Oscillators XOSC crystal oscillator is disabled When MCU ATSAML21 is in Active Performance Level 2 PL2 mode the DFLL48M is running at 48 MHz in Op...

Page 40: ...tting 25 16 88 IRX_ON PL0 RX_PDT_LEVEL 0x0 BPSK 20 fRF 868 3 MHz 10 79 PL2 RX_PDT_LEVEL 0x0 BPSK 20 fRF 868 3 MHz 16 47 IPLL_ON PL0 PLL_ON 6 41 PL2 PLL_ON 12 12 ITRX_OFF PL0 TRX_OFF 1 68 PL2 TRX_OFF 7 39 ISTANDBY Standby LPEFF Enable PD0 PD1 and PD2 in Retention state with RTC running on OSCULP32K Sleep 2 03 µA IBACKUP Backup with RTC running on OSCULP32K Sleep 0 77 Notes 1 These values are based ...

Page 41: ...utlined in the following figure The module pins are arranged with a 1 2 mm pitch distance The module is designed in a symmetric way Dimensions missing in the following figure can be considered as identical to the opposite side Figure 10 1 Module Bottom Dimensions Top View in CAD Perspective ATSAMR30M18A Mechanical Description 2018 2021 Microchip Technology Inc and its subsidiaries Datasheet DS7000...

Page 42: ... RF connection 10 2 Footprint The recommended land pattern is shown in the following figure Figure 10 2 Recommended Base Board Footprint ATSAMR30M18A Mechanical Description 2018 2021 Microchip Technology Inc and its subsidiaries Datasheet DS70005384B page 42 ...

Page 43: ...ble is used between the module RF output and the enclosure a unique nonstandard antenna connector must be used in the enclosure wall for interfacing with the antenna 3 Contact the antenna vendor for detailed antenna specifications to review suitability to end product operating environment and to identify equivalent alternatives 11 2 Module Assembly Considerations The ATSAMR30M18A module is assembl...

Page 44: ...race FEED POINT 1 NC 2 0900AT43A0070 A101 ANT_SUB_GHZ Trace Element 5 6nH L103 100n C104 VCC 12 GND 5 RESET 14 PA09 20 PA14 3 PA08 19 PA15 4 PA24 1 GND 13 PA18 8 PA25 2 PA16 6 PA17 7 GND 24 PA07 18 PA19 9 PA27 10 PA28 11 PA30 15 PA31 16 RF OUT 23 PA06 17 GND 22 GND 21 GND 25 U101 SAMR30 Module 7 5nH L101 INDUCTOR 3 3nH L102 INDUCTOR 1 5nH L104 12pF C101 12pF C102 GND 100R R106 100R R105 100R R104 ...

Page 45: ... on the SAMR30 Module XPRO Product web page Follow the module placement and RF trace design as in the following figure The module must be placed in the host board such that the chip antenna or the RF connector 1 is at one of the edges of the host PCB For a design with an external antenna through the RF connector 1 the RF trace running from L106 to chip antenna can be replaced with GND polygon pour...

Page 46: ...rence board focused on the RF traces The snapshot also indicates the critical dimensions that are required to be replicated in the design to maintain compliance Figure 12 4 Top Layer Layout ATSAMR30M18A Application Reference Design 2018 2021 Microchip Technology Inc and its subsidiaries Datasheet DS70005384B page 46 ...

Page 47: ... traces Figure 12 6 Bottom Layer Layout The following image shows the PCB stack up for the reference board Layer 1 Top Layer and Layer 2 specifications are critical to the RF Trace Layout specification ATSAMR30M18A Application Reference Design 2018 2021 Microchip Technology Inc and its subsidiaries Datasheet DS70005384B page 47 ...

Page 48: ...RF power through conducted measurement at junction between L106 and L105 3 Remove L106 and R115 to isolate the antenna path from the measurement point It is recommended that the measured TX power be within the data sheet specification for the Transmit output power For good measurement it is recommended that there be a firm connection between the copper core of the coaxial cable and the measurement...

Page 49: ...e files and gerber files are available for download from the SAMR30M Sensor board product page The following is a snapshot of the schematic diagram for the host SAMR30M Sensor board showing the PCB Antenna section Figure 12 9 PCB Antenna Trace layout dimensions Trace width 0 533 mm Trace gap 0 381 mm Finished copper thickness 47 µm Layout of Trace design The following figure shows the top layer ro...

Page 50: ...o indicates the critical dimensions that are required to be replicated in the design to maintain compliance Figure 12 11 Top Layer Layout of the Reference Board The following figure shows the bottom layer layout of the reference board directly beneath the RF traces ATSAMR30M18A Application Reference Design 2018 2021 Microchip Technology Inc and its subsidiaries Datasheet DS70005384B page 50 ...

Page 51: ...gure shows the PCB stack up for the reference board Layer 1 Top layer and Layer 2 specifications are critical to the RF Trace Layout specification ATSAMR30M18A Application Reference Design 2018 2021 Microchip Technology Inc and its subsidiaries Datasheet DS70005384B page 51 ...

Page 52: ...ations In a four or higher layer PCB design dedicate the layer immediately below the layer containing the ATSAMR30M18A module for GND Avoid routing any traces in the region on the top layer of the host board which will be directly below the module area Place GND polygon pour below the module covering the entire area Do not have any breaks in this GND plane Place sufficient GND vias in this polygon...

Page 53: ...is recommended that the antenna in the host board not be placed in direct contact or close proximity to plastic casing objects Keep a minimum clearance of 7 mm in all directions around the antenna Do not enclose the antenna in the host board within a metal shield Keep any components which may radiate noise or signals within the 850 950 MHz frequency band away from the antenna and if possible shiel...

Page 54: ...nd user This requirement needs to be taken care of via Host implementation 13 1 United States FCC The ATSAMR30M18A module has received Federal Communications Commission FCC CFR47 Telecommunications Part 15 Subpart C Intentional Radiators modular approval in accordance with Part 15 212 Modular Transmitter approval Modular approval allows the end user to integrate the ATSAMR30M18A module into a fini...

Page 55: ...eiver Connect the equipment into an outlet on a circuit different from that to which the receiver is connected Consult the dealer or an experienced radio TV technician for help Additional information on labeling and user information requirements for Part 15 devices can be found in KDB Publication 784748 which is available at the FCC Office of Engineering and Technology OET Laboratory Division Know...

Page 56: ...ost product must be labeled to display the Innovation Science and Economic Development Canada certification number of the module preceded by the word Contains or similar wording expressing the same meaning as follows For ATSAMR30M18A Contains IC 20266 R30M User Manual Notice for License Exempt Radio Apparatus from Section 8 4 RSS Gen Issue 5 February 2021 User manuals for license exempt radio appa...

Page 57: ...fic antenna tested in this application for certification and must not be co located or operating in conjunction with any other antenna or transmitters within a host device except in accordance with Canada multi transmitter product procedures The device operates at an output power level which is within ISED SAR test exemption limits at any user distance 13 2 3 Approved Antennas The testing of the A...

Page 58: ...2 of the RED is required 13 3 2 1 Simplified EU Declaration of Conformity Hereby Microchip Technology Inc declares that the radio equipment type ATSAMR30M18A is in compliance with Directive 2014 53 EU The full text of the EU declaration of conformity for this product is available at www microchip com wwwproducts en ATSAMR30M18 available under Documents Certifications 13 3 3 Approved Antennas The t...

Page 59: ... mode that directly uses the PLL signal without I Q modulation This is the recommended mode because the signal is placed at the selected channel center frequency FC and unwanted signal components are significantly lower PRBS mode requires data in the frame buffer that is a valid PHR followed by PSDU data After transmission of two non PSDU octets PSDU data is repeated continuously 14 2 Configuratio...

Page 60: ...ter access 0x1C W 0x54 11 Register access 0x1C W 0x46 12 Register access 0x02 W 0x09 Enable PLL_ON state 13 Interrupt event 0x0F R 0x01 Wait for IRQ_0 PLL_LOCK 14 Register access 0x02 W 0x02 Initiate transmission enter BUSY_TX state 15 Measurement Perform measurement 16 Register access 0x1C W 0x00 Disable Continuous Transmission Test Mode 17 Reset Reset AT86RF212B Table 14 2 Additional CW Mode Pro...

Page 61: ...t event 0x0F R 0x01 Wait for IRQ_0 PLL_LOCK 14 Register access 0x02 W 0x02 Initiate transmission enter BUSY_TX state 15 Measurement Perform measurement 16 Register access 0x1C W 0x00 Disable Continuous Transmission Test Mode 17 Reset Reset AT86RF212B rev C 1 Changing the output power during continuous transmission is not allowed ATSAMR30M18A Continuous Transmission Test Mode Errata 2018 2021 Micro...

Page 62: ...works WPANs Amendment 2 Alternative Physical Layer Extension to support one or more of the Chinese 314 316 MHz 430 434 MHz and 779 787 MHz bands IEEE Standard 802 15 4 2011 Low Rate Wireless Personal Area Networks WPANs ATSAMR30E18A Data Sheet IEEE 802 15 4 Sub GHz System in Package Datasheet ATSAMR30M18A Product Page SAMR30 module s product page SAMR30 Module Xplained Pro Design Documentation Pro...

Page 63: ...sting software codes of this product are outdated and unsuitable This document may use these new terminologies which may or may not reflect on the source codes software GUIs and the documents referenced within this document The following table shows the relevant terminology changes made in this document Table 16 1 Terminology Related Changes Old Terminology New Terminology Section LIN Slave LIN Cl...

Page 64: ...ting of sales offices and locations is included in this document Technical support is available through the website at www microchip com support Microchip Devices Code Protection Feature Note the following details of the code protection feature on Microchip devices Microchip products meet the specifications contained in their particular Microchip Data Sheet Microchip believes that its family of pr...

Page 65: ...r QTouch SAM BA SenGenuity SpyNIC SST SST Logo SuperFlash Symmetricom SyncServer Tachyon TimeSource tinyAVR UNI O Vectron and XMEGA are registered trademarks of Microchip Technology Incorporated in the U S A and other countries AgileSwitch APT ClockWorks The Embedded Control Solutions Company EtherSynch FlashTec Hyper Speed Control HyperLight Load IntelliMOS Libero motorBench mTouch Powermite 3 Pr...

Page 66: ...ement System For information regarding Microchip s Quality Management Systems please visit www microchip com quality ATSAMR30M18A 2018 2021 Microchip Technology Inc and its subsidiaries Datasheet DS70005384B page 66 ...

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