Micrel KSZ8081MNX User Manual Download | Manualshive

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KSZ8081MNX-EVAL

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Summary of Contents for KSZ8081MNX

Page 1: ... for its use Micrel reserves the right to change circuitry and specifications at any time without notification to the customer Micrel Products are not designed or authorized for use as components in life support appliances devices or systems where malfunction of a product can reasonably be expected to result in personal injury Life support devices or systems are devices or systems that a are inten...

Page 2: ...KSZ8081MNX KSZ8091MNX 10Base T 100Base TX Evaluation Board User s Guide Micrel Inc August 15 2012 Rev 1 0 2 13 Revision History Revision Date Summary of Changes 1 0 8 15 12 Initial Release ...

Page 3: ...2 Rev 1 0 3 13 Table of Contents 1 0 Introduction 5 2 0 Board Features 5 3 0 Evaluation Kit Contents 5 4 0 Hardware Description 6 4 1 MII Media Independent Interface 7 4 2 Jumper Setting Definition 9 4 3 Test Point Definition 12 4 4 RJ 45 Connector 12 4 5 LED Indicators 12 5 0 Bill of Materials 13 ...

Page 4: ...es Table 1 Connector J2 MII Pin Definition 8 Table 2 KSZ8081MNX EVAL KSZ8091MNX EVAL Strapping Jumper Definition 9 Table 3 KSZ8081MNX EVAL KSZ8091MNX EVAL Loopback Jumper Definition 9 Table 4 KSZ8081MNX EVAL KSZ8091MNX EVAL Miscellaneous Jumper Definition 10 Table 5 Strapping Pin Definitions for KSZ8081MNX EVAL KSZ8091MNX EVAL Jumpers 11 Table 6 KSZ8081MNX EVAL KSZ8091MNX EVAL Test Point Definitio...

Page 5: ...device All configuration pins are accessible either by jumpers test points or interface connectors 2 0 Board Features Micrel KSZ8081MNX or KSZ8091MNX 10Base T 100Base TX Physical Layer Transceiver RJ 45 Jack for Fast Ethernet cable interface HP Auto MDI MDI X for automatic detection and correction for straight through and crossover cables MII Media Independent Interface Connector to interface with...

Page 6: ...tion of the KSZ8081MNX KSZ8091MNX is accomplished through on board jumper selections and or by PHY register access via the MDC MDIO management pins of the MII Interface Figure 1 KSZ8081MNX Evaluation Board Features include an RJ 45 Jack for Fast Ethernet cable connection programmable LED indicators for reporting link status and activity and a manual reset button for quick reboot after re configura...

Page 7: ... 802 3 Specification MII Management MIIM is conducted thru pins MDC clock line and MDIO data line MIIM allows upper layer devices to monitor and control the states of the KSZ8081MNX KSZ8091MNX An external device with MDC MDIO capability can be used to read the PHY status or configure the PHY registers The MIIM frame format and timing information can be found in the KSZ8081MNX and KSZ8091MNX datash...

Page 8: ...Ground 3 MDC 23 Ground 4 RXD3 24 Ground 5 RXD2 25 Ground 6 RXD1 26 Ground 7 RXD0 27 Ground 8 RXDV 28 Ground 9 RXCLK 29 Ground 10 RXER 30 Ground 11 TXER 31 Ground 12 TXCLK 32 Ground 13 TXEN 33 Ground 14 TXD0 34 Ground 15 TXD1 35 Ground 16 TXD2 36 Ground 17 TXD3 37 Ground 18 COL 38 Ground 19 CRS 39 Ground 20 5V 40 5V Table 1 Connector J2 MII Pin Definition ...

Page 9: ...2 0 Mode open open open MII default close close open MII Back to Back All other CONFIG 2 0 settings not listed are reserved not used J7 CONFIG1 J8 CONFIG2 J9 Isolate Mode Disable Enable J10 Nway Auto Negotiation Enable Disable J11 Forced Speed KSZ8081 only 100Base TX 10Base T J12 Forced Duplex Half Full J25 Broadcast Off for PHY Address 0 Broadcast PHY address Unique PHY address J26 PME_N Pin Enab...

Page 10: ...in 31 connection LED1 or TXER For KSZ8081 only pin 31 LED1 For KSZ8091 only pin 31 TXER Table 4 KSZ8081MNX EVAL KSZ8091MNX EVAL Miscellaneous Jumper Definition Table 5 lists the strapping pin definitions for the KSZ8081MNX EVAL KSZ8091MNX EVAL jumpers Jumper Pin Pin Name Pin Function J5 J4 J3 15 14 13 PHYAD2 PHYAD1 PHYAD0 The PHY Address is latched at power up reset and is configurable to any valu...

Page 11: ...N Nway Auto Negotiation Enable Pull up default Enable Auto Negotiation Pull down Disable Auto Negotiation At the de assertion of reset this pin value is latched into register 0h bit 12 J25 19 B CAST_OFF Broadcast Off for PHY Address 0 Pull up PHY Address 0 is set as a unique PHY address Pull down default PHY Address 0 is set as a broadcast PHY address At the de assertion of reset this pin value is...

Page 12: ...Ethernet cable to interface with 10Base T 100Base TX Ethernet devices 4 5 LED Indicators A dual LED indicator LED1 is located adjacent to the RJ 45 Connector The top LED and bottom LED are connected to LED1 pin 31 and LED0 pin 30 respectively The two LEDs are programmable to LED mode 00 or 01 via register 1Fh bits 5 4 and are defined in the following table LED Mode LED1 pin 31 LED0 pin 30 00 Speed...

Page 13: ...ack thru hole PC mount 11 1 J2 Male MII Connector PCB edge mount 12 18 J3 J4 J5 J6 J7 J8 J9 J10 Header 2X1 thru hole 0 1 pitch J11 J12 J13 J14 J16 J17 J18 J19 J25 J26 13 3 JP3 JP10 JP11 Header 3X1 thru hole 0 1 pitch 14 1 LED1 LEDx2 Green thru hole 0 1 pitch 15 1 R1 100K 0603 16 1 R2 10K 0603 17 9 R3 R25 R26 R27 R28 4 7K 0603 R29 R30 R102 R103 18 10 R4 R5 R6 R7 R8 R9 R16 33 0603 R17 R20 R21 19 1 R...

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