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6 Mykerinos Block Diagram
6.1 Mykerinos Block Diagram
SSI
SDRAM
Up to 32 MB
Trimedia
TM-1300
PLL
Video
Control Signals only
DIFFERENT SIGNALS
M
IN
I
D
IN
8
P
O
S
.
Figure 1 - Mykerinos Block Diagram
The Mykerinos board is based on the Philips Trimedia TM-1300 Chip and its associated SDRAM running at 144 MHz. The
other peripherals are:
•
1 FPGA (Field Programmable Gate Array), used to manage the control signals
•
1 Timecode reader – generator (LTC and VITC)
•
1 Video PLL, used to lock to any incoming Video reference such as black-burst PAL, NTSC or Tri-level HDTV
•
1 stereo 24 bit 96kHz D/A for onboard audio monitoring.
Up to 64 audio channels are conveyed over the Trimedia high-speed “Video IN” and “Video OUT” buses through connector
J4
to/from the specific I/O daughter card.
6.2 Mykerinos On-Board Connectors and Jumpers
The connectors implemented on the Mykerinos board are as follows:
•
JP1 -
header 1x2, Reserved.
•
JP2 -
Video/TC connector 8x2, offering the same functionalities as J2 but for internal connection
•
JP3 -
header 1x2, used to connect internally a Video Reference Sync (in lieu of CVS1IN signal)
•
J2
- 1 mini Din 8 pins, used to transfer Video and Timecode signals
•
J3 -
1 stereo headphone monitoring output 3.5mm mini-jack connector
•
J4 -
1 mezzanine connector 32x2, used to connect I/O daughter cards
•
JP4 -
75ohm termination for CVS1IN (input from J2, JP2 or JP3)
•
JP5 -
75ohm termination for WCKIO (input from J2 or JP2)
•
JP6 -
monitoring gain attenuation (-12dB when open) for the left channel
•
JP7 -
monitoring gain attenuation (-12dB when open) for the right channel
