Memotech Limited MTX 500, Service Manual

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IORQ.
Input/Output Request (output, active Low, 3-
state). IORQ indicates that the lower half of the
address bus holds a valid I/O address for an I/O
read or write operation. IORQ is also generated
concurrently with M1 during an interrupt
acknowledge cycle to indicate that an interrupt
response vector can be placed on the data bus.
M1.
Machine Cycle One (output, active Low). M1,
together with MREQ, indicates that the current
machine cycle is the opcode fetch cycle of an
instruction execution. M1, together with IORQ,
indicates an interrupt acknowledge cycle.
MREQ.
Memory Request (output, active Low, 3-state).
MREQ indicates that the address bus holds a valid
address for a memory read or memory write
operation.
NMI.
Non-Maskable Interrupt (input, negative edge-
triggered). NMI has a higher priority than INT.
NMI is always recognized at the end of the current
instruction, independent of the status of the
interrupt enable flip-flop, and automatically
forces the CPU to restart at location 0066H.
RD.
Read (output, active Low, 3-state). RD indicates
that the CPU wants to read data from memory or an
I/O device. The addressed I/O device or memory
should use this signal to gate data onto the CPU
data bus.
RESET.
Reset (input, active Low). RESET initialises the
CPU as follows: it resets the interrupt enable
flip-flop, clears the PC and Registers I and R,
and sets the interrupt status to Mode 0. During
reset time, the address and data bus go to a high-
impedance state, and all control output Signals go
to the inactive state. Note that RESET must be
active for a minimum of three full clock cycles
before the reset operation is complete.
MTX Service Manual