Measurement Computing USB-1808X, User Manual

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USB-1808X User's Guide Functional Details
14
Encoder input operations can be paced by the internal clock or by an external clock (
ICLKI
– refer to Clock I/O
on page 15). They can be initiated by a digital trigger ( Digital triggering on page 15) or a pattern trigger
(
Pattern triggering on page 15
).
Refer to
Synchronous I/O – mixing analog, digital, and counter scanning
on page 15 for information on running
quadrature encoder scans at the same time as other subsystem scans.
Each supported quadrature encoder option is explained in following table:
Quadrature encoder options
Encoder
option
Description
Count mode Select X1, X2, or X4. Count modes provide different levels of accuracy with respect to the encoder
position.

X1: counts rising edges on input A.

X2: counts rising edges and falling edges on input A.

X4: count rising and falling edges on both inputs A and B.
Range limit When counting up: The counter stops when the maximum count (specified by the MAXLIMIT
value) is reached. Counting resumes if direction is reversed or the counter is cleared.
When counting down: The counter stops when the minimum count (specified by the MINLIMIT
value) is reached. Counting resumes if direction is reversed or the counter is cleared.
Quadrature encoder options that are specific to the Z signal (ENCxZ) are is explained in following table.
Z input quadrature encoder options ()
Counter mode Description
Clear on Z The counter is cleared by the Z signal.
Latching Latching mode allows the count to be latched by the Z signal.
Timer output
You can use
TMR0
through
TMR1
as 32-bit timer outputs. Each timer can generate pulse rates of up to 50 MHz,
with programmable pulse widths down to 10 ns.
The timer output rate and pulse width can be updated asynchronously at any time, however, doing so results in a
pulse stream that is not seamless.
The following timer output options are software-selectable:

pulse frequency

duty cycle (pulse width divided by the pulse period)

number of pulses to generate

time delay before starting the timer output after it is enabled

idle state of the output (idle high or idle low)
The time delay can range from 0 seconds to 42.94 seconds.
Figure 8. USB-1808X PWM timer channel
Timer output operations can be paced by the internal clock or by an external clock (
OCLKI
– refer to Clock I/O
on page 15). They can be initiated by a digital trigger ( Digital triggering on page 15).