Measurement Computing PCI-DAS1200/JR, User Manual

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PCI-DAS1200/JR User's Guide Specifications
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Digital input/output
Table 2. DIO specifications
Parameter Specification
Digital type 82C55A
Configuration 2 banks of 8, 2 banks of 4, programmable by bank as input or output
Number of I/O 24 (FIRSTPORTA 0 through FIRSTPORTC 7)
Output high 3.0 volts @ -2.5 mA min
Output low 0.4 volts @ 2.5 mA max
Input high 2.0 volts min, Vcc+0.5 volts absolute max
Input low 0.8 volts max, GND-0.5 volts absolute min
Power-up / reset state Input mode (high impedance)
Interrupts INTA# - mapped to IRQn via PCI BIOS at boot-time
Interrupt enable Programmable
Interrupt sources Residual counter, End-of-channel-scan, AD-FIFO-not-empty, AD-FIFO-half-full
Counter section
Table 3. Counter specifications
Parameter Specification
Counter type 82C54
Configuration Two 82C54 devices. 3 down counters per 82C54, 16 bits each
82C54A:
Counter 0 - ADC residual
sample counter.

Source: ADC Clock.

Gate: Internal programmable source.

Output: End-of-Acquisition interrupt.
Counter 1 - ADC pacer lower
divider

Source: 10 MHz oscillator

Gate: tied to counter 2 gate, programmable source.

Output: chained to counter 2 clock.
Counter 2 - ADC pacer upper
divider

Source: counter 1 output.

Gate: Tied to counter 1 gate, programmable source.

Output: ADC pacer clock (if software selected), available at user connector.
82C54B:
Counter 0 - pretrigger mode 
Source: ADC clock

Gate: external trigger

Output: End-of-Acquisition interrupt
Counter 0 - user counter 4
(when in non-pretrigger mode)

Source: User input at 100-pin connector (CLK4) or internal 10 MHz (software
selectable)

Gate: user input at 100-pin connector (GATE4)

Output: available at 100-pin connector (OUT4)
Counter 1 - user counter 5 
Source: user input at 100-pin connector (CLK5)

Gate: user input at 100-pin connector (GATE5)

Output: available at 100-pin connector (OUT5)
Counter 2 - user counter 6 
Source: user input at 100-pin connector (CLK6)

Gate: user input at 100-pin connector (GATE6)

Output: available at 100-pin connector (OUT6)
Clock input frequency 10 MHz max
High pulse width (clock input) 30 ns min
Low pulse width (clock input) 50 ns min
Gate width high 50 ns min
Gate width low 50 ns min
Input low voltage 0.8 V max