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AT INTERFACE DESCRIPTION

5 – 2

Pin Description Table

Pin Description Table

Pin Description Table

Pin Description Table

Pin Description Table

PIN  NAME

PIN

I/O

SIGNAL  NAME

SIGNAL  DESC RIPTION

RESET  -

01

I

Hos t  Reset

Reset si gnal from the host s ystem. Acti ve during power up and inacti ve afte

D D0

17

I/O

Host  Data  Bus

16 bit bi-directional data  bus between host and dri ve. Lower 8 bi ts used for

register  and EC C  byte  transfers. All  16  bi ts us ed for  data transfers.

D D1

15

I/O

D D2

13

I/O

D D3

11

I/O

D D4

09

I/O

D D5

07

I/O

D D6

05

I/O

D D7

03

I/O

D D8

04

I/O

D D9

06

I/O

DD 10

08

I/O

D D11

10

I/O

DD 12

12

I/O

DD 13

14

I/O

DD 14

16

I/O

DD 15

18

I/O

D MARQ21

O

DM A  Request

This  signal is used wi th DM AC K for D MA transfers .  By asser ti ng thi s s ignal

dri ve indi cates that data is ready to  be transfered to and from the host.

DIOW  -

STOP

23

I

Host I/O Write

Risi ng edge of Wr ite strobe clock s data from  the  hos t  data bus to a regi ster

the drive.

D IOR  -

HD MARDY

-

HSTROBE

25

I

Host I/O Read

Read strobe enabl es  data from a register on  the  dri ve onto the  host data b u
DMA  ready duri ng UltraDMA data  in bursts.
Data  strobe during  UltraDMA  data out bursts.

IORDY

DD MARDY

-

DSTROBE

27

O

I/O C hannel Ready

This signal may be  driven low by the dri ve to insert wait states  into host  I/O

cycles.
D MA ready duri ng  UltraDMA  data out bursts.
D ata str obe during Ul traDMA data  in bursts.

CSEL

28

C able Select

Us ed for  Mas ter/Slave  selection via cabl e. Requires s peci al cabling on host
s ystem and i nstallation  of C abl e  Sel ect jumper.

D MACK  -

29

I

D MA Acknowledge

This  signal is used wi th DM ARQ for D MA transfers .  By asser ti ng thi s s ignal

host  is  ac knowledging the recei pt  of data  or  i s indicating that data  is  availa

INTRQ31

O

Hos t  Interrupt
Request

Interrupt to the host asserted when the dri ve  requi res attenti on from the host

IOC S16

32

D evi ce 16 bit  I/O

Obsolete

PD IAG  -

34

I/O

Pas sed D i agnostic

Output by dri ve when  in Slave mode;  Input to drive when in  Master mode.

DA0

35

I

Hos t  Address  Bus

3 bi t binary  address from  the  host to  selec t  a  regis ter in the dri ve.

DA1

33

I

DA2

36

I

C S0  -

37

I

Host Chip Select 0

C hi p  sel ec t  from the host used to access the C omm and Bl ock  registers in th
dri ve. Thi s si gnal i s a decode of I/O addres ses  1F0 -  1F 7  hex.

C S1  -

38

I

Host Chip Select 1

Chip select from the host  used  to access  the  Control registers  in the drive. T
si gnal is a decode of I/O addres ses  3F6 -  3F 7  hex.

DASP  -

39

I/O

Drive Active/D ri ve

1 Present

Ti me-multiplexed, open  collector output  whi ch i ndi cates that a drive i s active
that

device 1 is pres ent.

GND

02

N/A

Ground

Si gnal ground.

Summary of Contents for 4W030H2

Page 1: ...in the product s described in this publication at any time and without notice Copyright 2001 Maxtor Corporation All rights reserved Maxtor MaxFax and No Quibble Service are registered trademarks of Maxtor Corporation Other brands or products are trademarks or registered trademarks of their respective holders Corporate Headquarters 510 Cottonwood Drive Milpitas California 95035 Tel 408 432 1700 Fax...

Page 2: ...static discharge ESD precautions includingpersonnelandequipmentgrounding Stand alonedrivesare sensitive to ESD damage 2 2 2 2 2 BEFORE removing drives from their packing material allow them to reach room temperature 3 3 3 3 3 During handling NEVER drop jar or bump a drive 4 4 4 4 4 Once a drive is removed from the Maxtor shipping container IMMEDIATELY secure the drive through its mounting holes wi...

Page 3: ...rding 2 2 Read Write Multiple Mode 2 2 Ultra ATA Mode 5 2 2 Multi word DMA EISA Type B Mode 2 2 2 Sector Address Translation 2 2 Logical Block Addressing 2 3 Defect Management Zone 2 3 On the Fly Hardware Error Correction Code ECC 2 3 Software ECC Correction 2 3 Automatic Head Park and Lock Operation 2 3 Cache Management 2 4 Buffer Segmentation 2 4 Read Ahead Mode 2 4 Automatic Write Reallocation ...

Page 4: ...e 3 4 EMC EMI 3 5 EMC Compliance 3 5 Canadian Emissions Statement 3 5 Safety Regulatory Compliance 3 5 Section 4 Section 4 Section 4 Section 4 Section 4 Handling and Installation Handling and Installation Handling and Installation Handling and Installation Handling and Installation Hard Drive Handling Precautions 4 1 Electro Static Discharge ESD 4 1 Unpacking and Inspection 4 2 Repacking 4 3 Physi...

Page 5: ...Sector Number Register 6 2 Cylinder Number Registers 6 2 Device Head Register 6 2 Status Register 6 2 Command Register 6 3 Read Commands 6 3 Write Commands 6 3 Mode Set Check Commands 6 3 Power Mode Commands 6 3 Initialization Commands 6 3 Seek Format and Diagnostic Commands 6 3 S M A R T Commands 6 3 Summary 6 4 Control Diagnostic Registers 6 5 Alternate Status Register 6 5 Device Control Registe...

Page 6: ...le Immediate 7 8 Standby 7 8 Idle 7 8 Check Power Mode 7 8 Set Sleep Mode 7 8 Default Power on Condition 7 9 Initialization Commands 7 10 Identify Drive 7 10 Initialize Drive Parameters 7 13 Seek Format and Diagnostic Commands 7 14 S M A R T Command Set 7 15 Section 8 Section 8 Section 8 Section 8 Section 8 Service and Support Service and Support Service and Support Service and Support Service and...

Page 7: ...ta Transfer to from Device 5 3 5 3 Multi word DMA Data Transfer 5 4 5 4 Initiating an Ultra DMA Data In Burst 5 5 5 5 Sustained Ultra DMA Data In Burst 5 6 5 6 Host Pausing an Ultra DMA Data In Burst 5 6 5 7 Device Terminating an Ultra DMA Data In Burst 5 7 5 8 Host Terminating an Ultra DMA Data In Burst 5 7 5 9 Initiating an Ultra DMA Data Out Burst 5 8 5 10 Sustained Ultra DMA Data Out Burst 5 8...

Page 8: ... puts you in touch with either technical support or customer service We ll provide you the information you need quickly accurately and in the form you prefer a fax a downloaded file or a conversation with a representative ManualOrganization ManualOrganization ManualOrganization ManualOrganization ManualOrganization This hard disk drive reference manual is organized in the following method Section ...

Page 9: ...ions Signal Conventions Signal Conventions Signal Conventions Signal Conventions Signal names are shown in all uppercase type All signals are either high active or low active signals A dash character at the end of a signal name indicates that the signal is low active A low active signal is true when it is below ViL and is false when it is above ViH A signal without a dash at the end indicates that...

Page 10: ...ransfer rates 5400 RPM spin speed and 11 ms access times make these capacity class disk drives especially well suited to general desktop storage applications Key Features Key Features Key Features Key Features Key Features ANSI ATA 5 6 compliant PIO Mode 5 interface Enhanced IDE Supports Ultra DMA Mode 5 for up to 100 MBytes sec data transfers 2 MB buffer with multi adaptive cache manager 5400 RPM...

Page 11: ... 2 Supports multi word Direct Memory Access DMA EISA Type B mode transfers Sector Address Translation Sector Address Translation Sector Address Translation Sector Address Translation Sector Address Translation All Maxtor hard drives feature a universal translate mode In an AT EISA class system the drive may be configured to any specified combination of cylinders heads and sectors within the range ...

Page 12: ...gmentation Buffer Segmentation Buffer Segmentation Buffer Segmentation The data buffer is organized into two segments the data buffer and the micro controller scratch pad The data buffer is dynamically allocated for read and write data depending on the commands received A variable number of read and write buffers may exist at the same time Read Ahead Mode Read Ahead Mode Read Ahead Mode Read Ahead...

Page 13: ...the read write heads provides up to eight head selection depending on the model read pre amplification and write drive circuitry Read Write Heads and Media Read Write Heads and Media Read Write Heads and Media Read Write Heads and Media Read Write Heads and Media Low mass low force giant magneto resistive read write heads record data on 3 5 inch diameter disks Maxtor uses a sputtered thin film med...

Page 14: ... be accessed via a common interface cable using the same range of I O addresses The drives are jumpered as device 0 or 1 Master Slave and are selected by the drive select bit in the Device Head register of the task file All Task File registers are written in parallel to both drives The interface processor on each drive decides whether a command written to it should be executed this depends on the ...

Page 15: ...n2 m ax ID OD 22 9 19 3 Trac k Density ktpi 52 Recording Density kbpi ID OD 440 354 Bytes per Sector Block 512 Sectors per Track ID OD 403 709 Sectors per Drive 195 711 264 160 086 528 120 103 200 80 043 264 60 030 432 MODELS 4W100H6 4W080H6 4W060H4 4W040H3 4W030H2 Seek Times typi cal read m s Track to Track 1 Average normal seek 11 Full Stroke normal seek 20 Average Latency m s 5 55 Controller Ov...

Page 16: ...ysicalDimensions PhysicalDimensions PhysicalDimensions PhysicalDimensions PhysicalDimensions Figure3 1 OutlineandMountingDimensions PARAMETER VALUE Height max mm 26 1 Width typi cal mm 101 6 Length max mm 147 0 Weight m ax kg 0 580 ...

Page 17: ...leep Sleep Sleep Sleep Sleep This is the lowest power state with the interface set to inactive A software or hardware reset is required to return the drive to the Standby state EPA Energy Star Compliance EPA Energy Star Compliance EPA Energy Star Compliance EPA Energy Star Compliance EPA Energy Star Compliance Maxtor Corporation supports the goals of the U S Environmental Protection Agency s Energ...

Page 18: ...cles 50 000 Average minimum cycles for reliable start stop function Data Reliability Data Reliability Data Reliability Data Reliability Data Reliability 1 per 10E15 bits read Data errors non recoverable Average data error rate allowed with all error recovery features activated Component Design Life Component Design Life Component Design Life Component Design Life Component Design Life 5 years mini...

Page 19: ...lled in a typical personal computer Maxtor recommends that testing and analysis for EMC compliance be performed with the disk mechanism installed within the user s end use application Canadian Emissions Statement Canadian Emissions Statement Canadian Emissions Statement Canadian Emissions Statement Canadian Emissions Statement This digital apparatus does not exceed the Class B limits for radio noi...

Page 20: ... drive baseplate Electro Static Discharge ESD Electro Static Discharge ESD Electro Static Discharge ESD Electro Static Discharge ESD Electro Static Discharge ESD To avoid some of the problems associated with ESD Maxtor advises that anyone handling a disk drive use a wrist strap with an attached wire connected to an earth ground Failure to observe these precautions voids the product warranty Manufa...

Page 21: ... reuse Inspect the shipping container for evidence of damage in transit Notify the carrier immediately in case of damage to the shipping container As they are removed inspect drives for evidence of shipping damage or loose hardware If a drive is damaged and no container damage is evident notify Maxtor immediately for drive disposition Figure4 1 Multi packShippingContainer ...

Page 22: ...mmended Mounting Configuration Recommended Mounting Configuration Recommended Mounting Configuration Recommended Mounting Configuration Recommended Mounting Configuration The Maxtor hard drive design allows greater shock tolerance than that afforded by larger heavier drives The drive may be mounted in any attitude using four size 6 32 screws with 1 8 inch maximum penetration and a maximum torque o...

Page 23: ... larger than 8 4 GB Pentium class processor Operating System Requirements Operating System Requirements Operating System Requirements Operating System Requirements Operating System Requirements Drives less than or equal to 8 4 GB DOS 5 0 or higher Drives larger than 8 4 GB Installing as boot drive Primary Master requires full installation set of Windows 95 98 not an update from DOS or Windows 3 x ...

Page 24: ... the Maxtor drive This connector is keyed and will only fit one way Check all other cable connections before you power up Striped colored edge is pin 1 AfterattachingtheIDEinterfacecableandthe powercabletotheMaxtorharddrive verifythat allothercablesconnectedtootherdevices the motherboardorinterfacecard s arecorrectly seated Striped colorededgeispin Start up Start up Start up Start up Start up Turn...

Page 25: ...commodate a cable connection maximum cable length 18 inches Figure5 1 DataConnector Pin Description Summary Pin Description Summary Pin Description Summary Pin Description Summary Pin Description Summary PIN SIGNAL PIN SIGNAL 01 Reset 02 Ground 03 DD7 04 DD8 05 DD6 06 DD9 07 DD5 08 DD10 09 DD4 10 DD11 11 DD3 12 DD12 13 DD2 14 DD13 15 DD1 16 DD14 17 DD0 18 DD15 19 Ground 20 keypin 21 DMARQ 22 Groun...

Page 26: ...eady This signal may be driven low by the drive to insert wait states into host I O cycles DMA ready during UltraDMA data out bursts Data strobe during UltraDMA data in bursts CSEL 28 Cable Select Used for Master Slave selection via cable Requires special cabling on host system and installation of Cable Select jumper DMACK 29 I DMA Acknowledge This signal is used with DMARQ for DMA transfers By as...

Page 27: ...30 ns 20 ns t4 DIOW data hold min 30 ns 20 ns 15 ns 10 ns 10 ns t5 DIOR data setup min 50 ns 35 ns 20 ns 20 ns 20 ns t6 DIOW data hold min 5 ns 5 ns 5 ns 5 ns 5 ns t6Z DIOR data tristate max 30 ns 30 ns 30 ns 30 ns 30 ns t9 DIOR DIOW to address valid hold min 20 ns 15 ns 10 ns 10 ns 10 ns tRd Read Data Valid to IORDY active min 0 0 0 0 0 tA IORDY Setup Time 35 ns 35 ns 35 ns 35 ns 35 ns tB IORDY P...

Page 28: ...a hold min 5 ns 5 ns 5 ns tG DIOR DIOW data setup min 100 ns 30 ns 20 ns tH DIOW data hold min 20 ns 15 ns 10 ns tI DMACK to DIOR DIOW setup min 0 0 0 tJ DIOR DIOW to DMACK hold min 20 ns 5 ns 5 ns tKr DIOR negated pulse width min 50 ns 50 ns 25 ns tKw DIOW negated pulse width min 215 ns 50 ns 25 ns tLr DIOR to DMARQ delay max 120 ns 40 ns 35 ns tLw DIOW to DMARQ delay max 40 ns 40 ns 35 ns tZ DMA...

Page 29: ...I Unlimited interlock time 0 0 0 0 0 tAZ Maximum time allowed for outputs to release 10 10 10 10 10 tZAH Minimum delay time required for output drivers turning on from released state 20 20 20 20 20 tZAD 0 0 0 0 0 tENV Envelope time all control signal transitions are within the DMACK envelope by this much time 20 70 20 70 20 70 20 55 20 55 tSR STROBE to DMARDY response time to ensure the synchronou...

Page 30: ... tDVH DSTROBE at device DD 15 0 at device DSTROBE at host DD 15 0 at host tDVH tCYC tCYC tDVS tDVS tDH tDS tDH tDS t2CYC tDH tDVH t2CYC DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 device tSR tRFS tRP Figure5 6 HostPausinganUltraDMADataInBurst ...

Page 31: ...1 DA2 CS0 CS1 tACK tLI tMLI tDVS tLI tACK tACK tZAH tDVH tSS tLI Figure5 7 DeviceTerminatinganUltraDMADataInBurst tDVH CRC tAZ DMARQ device DMACK host STOP host HDMARDY host DSTROBE device DD 15 0 DA0 DA1 DA2 CS0 CS1 tACK tMLI tLI tLI tIORDYZ tACK tACK tZAH tMLI tDVS tRFS tRP Figure5 8 HostTerminatinganUltraDMADataInBurst ...

Page 32: ...15 0 at device tDVH tCYC tCYC tDVS tDVS tDS tDH t2CYC tDH tDVH t2CYC DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tUI tACK tENV tZIORDY tLI tDVS tDVH tACK tACK tUI Figure5 9 InitiatinganUltraDMADataOutBurst Figure5 10 SustainedUltraDMADataOutBurst ...

Page 33: ...OBE host DD 15 0 host tSR tRFS tRP Figure5 11 DevicePausinganUltraDMADataOutBurst DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tACK tLI tMLI tDVS tLI tLI tACK tIORDYZ tACK CRC tDVH tSS Figure5 12 HostTerminatinganUltraDMADataOutBurst ...

Page 34: ...PTION 5 10 DMARQ device DMACK host STOP host DDMARDY device HSTROBE host DD 15 0 host DA0 DA1 DA2 CS0 CS1 tACK tMLI tDVS tLI tLI tACK CRC tDVH tACK tIORDYZ tMLI tRP tRFS Figure5 13 DeviceTerminatinganUltraDMADataOutBurst ...

Page 35: ...or Register A read only register containing specific information regarding the previous command Data interpretation differs depending on whether the controller is in operational or diagnostic mode A power up reset software reset or receipt of a diagnostic command sets the controller into diagnostic mode This mode invalidates contents of the Status register The contents of the Error register reflec...

Page 36: ...ect LBA Mode Enabling this bit for commands not supported by LBA mode will abort the selected command When set the Task File register contents are defined as follows for the Read Write and translate command CONTENTS LBA BITS Sector Number 0 7 Cylinder Low 8 15 Cylinder High 16 23 Drive Head 24 27 Drive Select Set to 0 to select the master drive set to 1 to select the slave drive Head Select Specif...

Page 37: ...ong retries disabled Write Verify Sector s 3Ch Write Sector Buffer E8h Write Multiple C5h Write DMA CAh CBh No retries Mode Set Check Commands Mode Set Check Commands Mode Set Check Commands Mode Set Check Commands Mode Set Check Commands Set Features EFh Set Multiple Mode C6h Read Native Max Address F8h Set Max Mode F9h Power Mode Commands Power Mode Commands Power Mode Commands Power Mode Comman...

Page 38: ... Y Y Y Y Format Track 0 1 0 1 0 0 0 0 N N N Y Y Seek 0 1 1 1 x x x x N N Y Y Y Execute D iagnostic 1 0 0 1 0 0 0 0 N N N N D Initialize Parameters 1 0 0 1 0 0 0 1 N Y N N Y Read Sector Buffer 1 1 1 0 0 1 0 0 N N N N D Write Sector Buffer 1 1 1 0 1 0 0 0 N N N N D Identify Drive 1 1 1 0 1 1 0 0 N N N N D Set Features 1 1 1 0 1 1 1 1 Y N N N D Read Multiple 1 1 0 0 0 1 0 0 N Y Y Y Y Write Multiple 1...

Page 39: ... holds the drive in the reset state Clearing the bit re enables the drive The software Reset bit must be held active for a minimum of 5 µsec IRQ Enable Setting the Interrupt Request Enable to 0 enables the IRQ 14 signal to the host When this bit is set to 1 IRQ14 is tri stated and interrupts to the host are disabled Any pending interrupt occurs when the bit is set to 0 The default state of this bi...

Page 40: ...register The Busy bit does not clear until the reset clears and the drive completes initialization Completion of a reset operation does not generate a host interrupt Task File registers are initialized as follows Error 1 Sector Count 1 Sector Number 1 Cylinder Low 0 Cylinder High 0 Drive Head 0 Interrupt Handling Interrupt Handling Interrupt Handling Interrupt Handling Interrupt Handling The drive...

Page 41: ...ommands Write Commands Write Commands Write Sector s Write Verify Sector s Write Sector Buffer Write DMA Multi word DMA Ultra DMA Write Multiple Mode Set Check Commands Mode Set Check Commands Mode Set Check Commands Mode Set Check Commands Mode Set Check Commands Set Features Mode Set Multiple Mode Set Max Mode Read Native Max Address Power Mode Commands Power Mode Commands Power Mode Commands Po...

Page 42: ...k registers contain the numbers of the cylinder head and sector of the last sector read Back to back sector read commands set DRQ and generate an interrupt when the sector buffer is filled at the completion of each sector The drive is then ready for the data to be read by the host DRQ is reset and BSY is set immediately when the host empties the sector buffer If an error occurs during Read Sector ...

Page 43: ...ecution is also similar to that of the READ SECTOR S command except that 1 Several sectors are transferred to the host as a block without intervening interrupts 2 DRQ qualification of the transfer is required only at the start of each block not of each sector The block count consists of the number of sectors to be transferred as a block The block count is programmed by the Set Multiple Mode comman...

Page 44: ...number of the last sector written The next time the buffer is ready to be filled during back to back Write Sector commands DRQ is set and an interrupt is generated After the host fills the buffer DRQ is reset and BSY is set If an error occurs Write Sector operations terminate at the sector containing the error The Command Block registers then contain the numbers of the cylinder head and sector whe...

Page 45: ...e Multiple commands report after the attempted disk write of the block or partial block in which the error occurred The write operation ends with the sector in error even if it was in the middle of a block When an error occurs subsequent blocks are not transferred When DRQ is set at the beginning of each full and partial block interrupts are generated Write DMA Write DMA Write DMA Write DMA Write ...

Page 46: ... 03h Set Transfer Mode based on value in Sector Count register 05h Enable Advanced Power Management 42h Enable Automatic Acoustic Management The sector count register contains the Automatic Ac oustic Management level SECTOR LEVEL FFh Maxtor specific FEh Maximum performance 81h FDh Intermediate acoustic management levels 80h Minimum acoustic emanation level 00h 7Fh reserved 44h Length of data appen...

Page 47: ...Set Max Lock Set Max Lock Set Max Lock Set Max Lock After this sub command is completed any other SET MAX commands except SET MAX UNLOCK and SET MAX FREEZE LOCK are rejected The drive remains in this state until a power cycle or the acceptance of a SET MAX UNLOCK or SET MAX FREEZE LOCK command Set Max Unlock Set Max Unlock Set Max Unlock Set Max Unlock Set Max Unlock This sub command requests a tr...

Page 48: ...the Automatic Power Down sequence Idle 97h E3h Idle 97h E3h Idle 97h E3h Idle 97h E3h Idle 97h E3h Spin up and change time out value This command will spin up the spin motor if the drive is spun down If the drive is already spinning the spin up sequence is not executed A non zero value placed in the Sector Count register will enable the Automatic Power Down sequence and their timer will begin coun...

Page 49: ... the value placed in the Sector Count register is multiplied by five seconds to obtain the Time out Interval value If no drive commands are received from the host within the Time out Interval the drive automatically enters the STANDBY mode The minimum value is 5 seconds While the drive is in STANDBY MODE any commands received from the host are accepted and executed as they would in normal operatio...

Page 50: ...ATAPI 14 8 retired 7 1 removable media device 6 1 not removable controller and or device 5 3 retired 2 response incomplete 1 retired 0 reserved 1 Number of logical cylinders 2 Reserved 3 Number of logical heads 4 5 Retired 6 Number of logical sectors per logical track 7 8 Reserved 9 Retired 10 19 Drive serial number 20 ASCII characters 20 21 Retired 22 Obsolete 23 26 Firmware revision 8 ASCII char...

Page 51: ...rd DMA mode 1 and below are supported 0 1 Multi word DMA mode 0 is supported 7 0 Multi word DMA transfer modes supported 64 15 8 reserved 7 0 advanced PIO transfer modes supported 65 Minimum multi word DMA transfer cycle time per word 15 0 cycle time in nanoseconds 66 Manufacturer s recommeded multi word DMA transfer cycle time 15 0 cycle time in nanoseconds 67 Minimum PIO transfer cycle time with...

Page 52: ...ty Mode feature set enabled 0 1 SMART feature set enabled 86 Command sets s upported If words 82 and 83 0000h or FFFFh command set notification not supported 15 10 as c urrently defined 9 1 Automatic Acoustic Management feature set supported 8 0 as currently defined 88 Ultra DMA 15 14 reserved 13 1 Ultra DMA mode 5 is selected 0 Ultra DMA mode 5 is not selected 12 1 Ultra DMA mode 4 is selected 0 ...

Page 53: ... the number of logical cylinders Upon receipt of the command the drive 1 Sets BSY 2 Saves the parameters 3 Resets BSY and 4 Generates an interrupt To specify maximum heads write 1 less than the maximum e g write 4 for a 5 head drive To specify maximum sectors specify the actual number of sectors e g 17 for a maximum of 17 sectors track The sector count and head values are not checked for validity ...

Page 54: ...e buffer is full the drive resets DRQ sets BSY and begins command execution If the drive is not already on the desired track an implied seek is performed Once at the desired track the data fields are written with all zeroes Execute Drive Diagnostic Execute Drive Diagnostic Execute Drive Diagnostic Execute Drive Diagnostic Execute Drive Diagnostic Commands the drive to implement the internal diagno...

Page 55: ...ive codes are D0h S M A R T Read Attribute Value This feature returns 512 bytes of attribute information to the host D1h S M A R T Read Attribute Thresholds This feature returns 512 bytes of warranty failure thresholds to the host D2h Enable Disable Autosave To enable this feature set the sector count register to F1h enable or 0 disable Attribute values are automatically saved to non volatile stor...

Page 56: ...quired for repairs and returns Here s how it works 1 Customer calls 1 800 2MAXTOR for a Return Material Authorization RMA number and provides a credit card number 2 Maxtor ships a replacement drive within 2 business days and 3 Customer returns the original drive and credit card draft is destroyed Support Support Support Support Support Technical Assistance Technical Assistance Technical Assistance...

Page 57: ...or com Customer Service Customer Service Customer Service Customer Service Customer Service All Maxtor products are backed by No Quibble Service the benchmark for service and support in the industry Customer Service is available 5 a m to 5 p m Pacific Standard Time Monday through Friday U S and Canada Language support English Spanish Voice 800 2MAXTOR 800 262 9867 press 2 E mail RMA maxtor com Eur...

Page 58: ...cess time The average time to make all possible length accesses seeks average seek time The average time to make all possible length seeks A typical measure of performance B B B B B bad block A block that cannot store data because of a media flaw bit An abbreviation for binary digit of which there are two 0 and 1 A bit is the basic data unit of most digital computers A bit is usually part of a dat...

Page 59: ...e simultaneously under the set of read write heads This three dimensional storage volume can be accessed after a single seek cylinder zero The outermost cylinder in a drive that can be used for data storage D D D D D data An ordered collection of information In a specific case it is the information processed by a computer data separator An electronic circuit which decodes playback data and produce...

Page 60: ...rection code ECC A mathematical algorithm that can detect and correct errors in a data field This is accomplished with the aid of Check Bits added to the raw data error free A recording surface that has no defects error rate The number of errors type must be specified that occur in a specified number of bits read error recovery procedure The process that occurs in response to a data error In a dri...

Page 61: ...eference Used to update the physical disk address tracks and sectors of files and to expedite accesses inside diameter The smallest radial position used for the recording and playback of flux reversals on a magnetic disk surface initialization Applying input patterns or instructions to a device so that all operational parameters are at a known value input Data entering the computer to be processed...

Page 62: ...processor It is usually but not necessarily desktop size microprocessor A central processing unit CPU manufactured as a chip or a small number of chips missing pulse A term used in surface certification It is when a prerecorded signal is reduced in amplitude by a certain specified percentage modified frequency modulation MFM A method of encoding digital data signals for recording on magnetic media...

Page 63: ...are performed by the host processor using PIO register accesses to the data register plated thin film media Magnetic disk memory media having its surface plated with a thin coating of a metallic alloy instead of being coated with oxide processing The process of the computer handling manipulating and modifying data such as arithmetic calculation file lookup and updating and word pressing pulse crow...

Page 64: ...e read write head on track can be either open loop quasi closed loop or closed loop servo track A track on a servo surface The prerecorded reference track on the dedicated servo surface of a disk drive All data track positions are compared to their corresponding servo track to determine off track on track position settling time The time it takes a head to stop vibrating within specified limits aft...

Page 65: ... in question with or without repositioning the head V V V V V voice coil motor A positioning motor that uses the same principle as a voice coil in a loudspeaker The motor has no detent positions The mechanical motion output of it can be either rotary or linear W W W W W Whitney head A successor to the original Winchester read write head design The primary change was to make the flexure smaller and...

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