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MAX9777/MAX9778

Stereo 3W Audio Power Amplifiers with
Headphone Drive and Input Mux

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ELECTRICAL CHARACTERISTICS (continued)

(V

DD

= PV

DD

= 5.0V, GND = PGND = 0V, V

SHDN

= 5V, C

BIAS

= 1µF, R

IN

= R

F

= 15k

, R

L

. T

A

= T

MIN

to T

MAX

, unless otherwise

noted. Typical values are at T

A

= +25°C.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

2-WIRE SERIAL INTERFACE (SCL, SDA, ADD, 

INT

) (MAX9777)

Input-Voltage High

V

IH

2.6

V

Input-Voltage Low

V

IL

0.8

V

Input Hysteresis

0.2

V

Input High Leakage Current

I

IH

V

IN

 = 5V

±

1

µA

Input Low Leakage Current

I

IL

V

IN

 = 0V

±

1

µA

Input Capacitance

C

IN

10

pF

Output-Voltage Low

V

OL

I

OL

 = 3mA

0.4

V

Output Current High

I

OH

V

OH

 = 5V

1

µA

TIMING CHARACTERISTICS (MAX9777)

Serial Clock Frequency

f

SCL

400

kHz

Bus Free Time Between STOP
and START Conditions

t

BUF

1.3

µs

START Condition Hold Time

t

HD:STA

0.6

µs

START Condition Setup Time

t

SU:STA

0.6

µs

Clock Period Low

t

LOW

1.3

µs

Clock Period High

t

HIGH

0.6

µs

Data Setup Time

t

SU:DAT

100

ns

Data Hold Time

t

HD:DAT

(Note 3)

0

0.9

µs

Receive SCL/SDA Rise Time

t

r

(Note 4)

20 +

0.1C

B

300

ns

Receive SCL/SDA Fall Time

t

f

(Note 4)

20 +

0.1C

B

300

ns

Transmit SDA Fall Time

t

f

(Note 4)

20 +

0.1C

B

250

ns

Pulse Width of Suppressed
Spike

t

SP

(Note 5)

50

ns

Note 1:

All devices are 100% production tested at +25°C. All temperature limits are guaranteed by design.

Note 2:

Inputs AC-coupled to GND.

Note 3:

A master device must provide a hold time of at least 300ns for the SDA signal to bridge the undefined region of SCL’s
falling edge.

Note 4:

C

B

= total capacitance of one of the bus lines in picofarads. Device tested with C

B

= 400pF. 1k

pullup resistors connected

from SDA/SCL to V

DD

Note 5:

Input filters on SDA, SCL, and ADD suppress noise spikes of less than 50ns.

Note 6:

Headphone mode testing performed with 32

resistive load connected to GND. Speaker mode testing performed with 8

resistive load connected to GND. Mode transitions are controlled by 

SHDN

. KCP level is calculated as 20log[(peak voltage

during mode transition, no input signal)/1V

RMS

]. Units are expressed in dBV.

Summary of Contents for MAX9777

Page 1: ...external equalizer network The various functions are controlled by either an I2C compatible MAX9777 or simple parallel control interface MAX9778 The MAX9777 MAX9778 are available in a thermally effic...

Page 2: ...0 C to 85 C Storage Temperature Range 65 C to 150 C Junction Temperature 150 C Lead Temperature soldering 10s 300 C ELECTRICAL CHARACTERISTICS VDD PVDD 5 0V GND PGND 0V VSHDN 5V CBIAS 1 F RIN RF 15k R...

Page 3: ...jection Ratio Note 2 PSRR f 20kHz VRIPPLE 200mVP P 76 dB RL 32 88 Output Power POUT fIN 1kHz THD N 1 TA 25 C RL 16 200 mW POUT 60mW RL 32 0 002 Total Harmonic Distortion Plus Noise THD N fIN 1kHz BW 2...

Page 4: ...Condition Hold Time tHD STA 0 6 s START Condition Setup Time tSU STA 0 6 s Clock Period Low tLOW 1 3 s Clock Period High tHIGH 0 6 s Data Setup Time tSU DAT 100 ns Data Hold Time tHD DAT Note 3 0 0 9...

Page 5: ...AV 4V V POUT 250mW POUT 2W POUT 1W POUT 500mW TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY SPEAKER MODE MAX9777 78 toc05 FREQUENCY Hz THD N 10k 1k 100 0 01 0 1 1 0 001 10 100k RL 8 AV 2V V POUT...

Page 6: ...OWER W THD N 1 5 1 0 0 5 0 01 10 1 0 1 100 0 001 0 2 0 AV 4V V RL 8 f 20Hz f 1kHz f 10kHz OUTPUT POWER vs AMBIENT TEMPERATURE SPEAKER MODE MAX9777 78 toc13 AMBIENT TEMPERATURE C OUTPUT POWER W 60 35 1...

Page 7: ..._ AND OUT_ 1V div OUT_ OUT_ 500mV div SHDN 2V div TOTAL HARMONIC DISTORTION PLUS NOISE vs FREQUENCY HEADPHONE MODE MAX9777 78 toc22 FREQUENCY Hz THD N 10k 1k 100 0 001 0 01 0 1 1 0 0001 10 100k RL 16...

Page 8: ...BIENT TEMPERATURE C OUTPUT POWER mW 60 35 10 15 25 50 100 75 125 150 0 40 85 THD N 10 THD N 1 f 1kHz RL 32 OUTPUT POWER vs LOAD RESISTANCE HEADPHONE MODE MAX9777 78 toc32 LOAD RESISTANCE OUTPUT POWER...

Page 9: ...40 C Typical Operating Characteristics continued VDD PVDD 5V GND PGND 0V VSHDN 5V CBIAS 1 F TA 25 C unless otherwise noted POWER SUPPLY REJECTION RATIO vs FREQUENCY HEADPHONE MODE MAX9777 78 toc35 FRE...

Page 10: ...C unless otherwise noted SUPPLY CURRENT vs SUPPLY VOLTAGE HEADPHONE MODE MAX9777 78 toc40 SUPPLY VOLTAGE V SUPPLY CURRENT mA 5 25 5 00 4 75 2 4 6 8 10 12 0 4 50 5 50 TA 85 C TA 25 C TA 40 C POWER DISS...

Page 11: ...Address Select A logic high sets the address LSB to 1 a logic low sets the address LSB to zero 16 16 HPS Headphone Sense Input A logic high configures the device as a single ended headphone amp A logi...

Page 12: ...r into a 16 load with less than 1 THD N in headphone mode These devices also feature thermal overload protection BIAS These devices operate from a single 5V supply and fea ture an internally generated...

Page 13: ...de disables the interface and resets the I2C registers to a default state A logic high on SHDN enables the devices MAX9777 Software Shutdown A logic high on bit 0 of the SHDN register places the MAX97...

Page 14: ...requiring a pullup resistor 500 or greater to generate a logic high volt age Series resistors in line with SDA and SCL are option al These series resistors protect the input stages of the devices from...

Page 15: ...e MAX9777 generates an ACK when receiving an address or data by pulling SDA low during the night clock period When transmitting data the MAX9777 waits for the receiving device to generate an ACK Monit...

Page 16: ...ogic high selects input 1 a logic low selects input 2 Bit 2 HPS_D controls the headphone sensing A logic low configures the device in automatic headphone detection mode A logic high dis ables the HPS...

Page 17: ...are high impedance inputs SDA has an open drain that pulls the data line low during the ninth clock pulse The communication protocol supports the standard I2C 8 bit communications The general call ad...

Page 18: ...he BTL amplifier is disabled muting the speaker The gain is 1 2 that of the device in speaker mode and the output power is reduced by a factor of 4 In headphone mode the load must be capacitively coup...

Page 19: ...ire output coupling capacitors to operate in single ended headphone mode The output coupling capacitor blocks the DC component of the amplifier output preventing DC cur rent from flowing to the load T...

Page 20: ...low frequen cy response Figure 10 At low frequencies the capaci tor CF is an open circuit and the effective impedance in the feedback loop RF EFF is RF EFF RF1 At the frequency where the impedance CF...

Page 21: ...INRA GAINRB OUTR HPS VDD 4 5V TO 5 5V 4 5V TO 5 5V PVDD 4 5V TO 5 5V 0 1 F 17 5 6 19 20 28 1 15 2 14 16 22 21 24 26 12 10 7 8 11 25 3 4 Typical Application Circuits Stereo 3W Audio Power Amplifiers wi...

Page 22: ...__ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ _ HPF HPF MICROCONTROLLER CODEC MAX9778 INR2 INR1 INL2 INL1 BIAS 1 F 100 F 0 68 F 0 68 F 0 68 F 0 68 F 0 047 F 0 047 F 220 F 220 F 27 4k 27 4k 47k 10...

Page 23: ...MAX9777 2 1 INPUT MUX INL1 10k 0 1 F 1 F 100 F 0 68 F 15k 1k 15k 0 68 F 0 68 F 0 68 F 4 5V TO 5 5V PVDD VDD 3 4 8 7 10 12 15k 15k 33 2k 27 4k 10k 10k 0 047 F 220 F 220 F 33 2k 27 4k 0 047 F 22 21 24 2...

Page 24: ...1 INPUT MUX INL1 10k 0 1 F 1 F 100 F 0 68 F 15k 1k 15k 0 68 F 0 68 F 0 68 F 4 5V TO 5 5V PVDD VDD 3 4 8 7 10 12 15k 15k 33 2k 27 4k 10k 10k 0 047 F 220 F 220 F 33 2k 27 4k 0 047 F 22 21 24 26 16 11 25...

Page 25: ..._ __ __ __ _ 25 TOP VIEW MAX9777 THIN QFN 26 27 25 24 10 9 11 INT V DD INL1 INL2 GAINLA 12 SDA INR2 GND BIAS GAINRA HPS ADD 1 2 PVDD 4 5 6 7 20 21 19 17 16 15 OUTR PGND OUTL PVDD OUTL PGND V DD INR1 3...

Page 26: ..._ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ _ Package Information The p...

Page 27: ...change the circuitry and specifications without notice at any time Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 ____________________ 27 2006 Maxim Integrated Produc...

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