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MAX3421E Programming Guide
SAMPLEBUS
JSTATUS, KSTATUS
Meaning:
Sample the state of the USB bus.
SAMPLEBUS:
Sample the bus.
JSTATUS, KSTATUS:
Indicate the state.
Mode:
Host only
The CPU sets the SAMPLEBUS bit to instruct the SIE to sample the state of the D+ and D-
lines
.
The SIE clears the SAMPLEBUS bit when it completes the operation.
The JSTATUS bits are read-only, set and cleared by the SIE.
Programming Notes
The JSTATUS and KSTATUS bits update under two conditions:
1. The CPU sets SAMPLEBUS = 1
2. The CONDETIRQ asserts.
The second case indicates either a device attach or detach condition. The CPU should respond to
the CONDETIRQ by reading the JSTATUS and KSTATUS bits to determine which event
occurred.
The JSTATUS and KSTATUS bits are encoded as shown in Table 8.
Table 8. Encoding of the JSTATUS and KSTATUS Bits
JSTATUS KSTATUS
Meaning
0 0 SE0
0 1 K
1 0 J
1 1 N/A
The fourth entry in Table 8 is a non-defined USB bus condition.
Note:
The meaning of the J and K states depends on the setting of the LOWSPEED bit. When
LOWSPEED = 0, then J means D+ high and D- low; when LOWSPEED = 1, J means D+ low
and D- high.