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Maxim Dallas Semiconductor DS3171 General Description Manual Download Page 78

DS3171/DS3172/DS3173/DS3174 

 

 

78 

10.6  DS3/E3 Framer / Formatter 

10.6.1 General Description 

The Receive DS3/E3 Framer receives a unipolar DS3/E3 signal, determines frame alignment and extracts the 
DS3/E3 overhead in the receive direction. The Transmit DS3/E3 Formatter receives a DS3/E3 payload, generates 
framing, inserts DS3/E3 overhead, and outputs a unipolar DS3/E3 signal in the transmit direction. 

The Receive DS3/E3 Framer receives a DS3/E3 signal from the Receive LIU or RDATn (or RPOSn and RNEGn), 
determines the frame alignment, extracts the DS3/E3 overhead, and outputs the payload with frame and overhead  

The Transmit DS3/E3 Formatter receives a DS3/E3 payload on TSERn, generates a DS3/E3 frame, optionally 
inserts DS3/E3 overhead, and transmits the DS3/E3 signal. 

Refer to 

Figure 10-13

 for the location of the DS3/E3 Framer/Formatter blocks in the DS3174, 3, 2, 1 devices. 

Figure 10-13. Framer Detailed Block Diagram 

DS3/E3

Transmit

LIU

IEEE P1149.1

JTAG Test
Access Port

Microprocessor

Interface

HDLC

FEAC

LLB

DL

B

DS3 / E3

Transmit

Formatter

DS3 / E3

Receive

Framer

Trail

Trace

Buffer

DS3/E3

Receive

LIU

TAIS

TUA1

Clock Rate

Adapter

TX BERT

RX BERT

PLB

AL

B

UA1

GEN

B3ZS/

HDB3

Encoder

B3ZS/

HDB3

Decoder

 

10.6.2 Features 

10.6.2.1 Transmit Formatter 

• 

Programmable DS3 or E3 formatter

 – Accepts a DS3 (M23 or C-bit) or E3 (G.751 or G.832) signal and 

performs DS3/E3 overhead generation.

 

• 

Arbitrary framing format support

 – Generates a signal with an arbitrary framing format. The line 

overhead/stuff periods are added into the data stream using an overhead mask signal.

 

• 

Generates alarms and errors

 – DS3 alarm conditions (AIS, RDI, and Idle) and errors (framing, parity, and 

FEBE), or E3 alarm conditions (AIS and RDI/RAI) and errors (framing, parity, and REI) can be inserted into the 
outgoing data stream.

 

• 

Externally controlled serial DS3/E3 overhead insertion port

 – Can insert all DS3 or E3 overhead via a 

serial interface. DS3/E3 overhead insertion is fully controlled via the serial overhead interface.

 

• 

HDLC overhead insertion

 – An HDLC channel can be inserted into the DS3 or E3 data stream.

 

• 

FEAC insertion

 – A FEAC channel can be inserted into the DS3 or E3 data stream.

 

• 

Trail Trace insertion

 – Inputs and inserts the G.832 E3 TR byte. 

Summary of Contents for Dallas Semiconductor DS3171

Page 1: ...x 27mm 1 27mm pitch DS3174N 40 C to 85 C 400 TE PBGA 27mm x 27mm 1 27mm pitch Note Add the suffix for the lead free package option FUNCTIONAL DIAGRAM DS317x DS3 E3 PORTS DS3 E3 LIU DS3 E3 FRAMER FORM...

Page 2: ...174 quad perform framing formatting and line transmission and reception These devices contain integrated LIU s framer formatter for M23 DS3 C bit DS3 G 751 E3 G 832 E3 or a combination of the above si...

Page 3: ...SS VSS Figure 1 2 DS317x Functional Block Diagram RLCLKn RXPn RXNn TPOSn TDATn TNEGn TLCLKn Microprocessor Interface TXPn TXNn RDATn RNEGn RLCVn RST n port 1 4 D 15 0 A 10 1 ALE CS RD DS WR R W MODE I...

Page 4: ...AR CHANNEL MODE 20 7 MAJOR LINE INTERFACE OPERATING MODES 21 7 1 DS3HDB3 B3ZS AMI LIU MODE 21 7 2 HDB3 B3ZS AMI NON LIU LINE INTERFACE MODE 23 7 3 UNI LINE INTERFACE MODE 24 8 PIN DESCRIPTIONS 25 8 1...

Page 5: ...al Description 78 10 6 2 Features 78 10 6 3 Transmit Formatter 79 10 6 4 Receive Framer 79 10 6 5 C Bit DS3 Framer Formatter 83 10 6 6 M23 DS3 Framer Formatter 86 10 6 7 G 751 E3 Framer Formatter 88 1...

Page 6: ...T COMMON 134 12 3 1 Register Bit Descriptions 134 12 4 BERT 144 12 4 1 BERT Register Map 144 12 4 2 BERT Register Bit Descriptions 144 12 5 B3ZS HDB3 LINE ENCODER DECODER 152 12 5 1 Transmit Side Line...

Page 7: ...RACTERISTICS 220 18 AC TIMING CHARACTERISTICS 222 18 1 FRAMER AC CHARACTERISTICS 224 18 2 LINE INTERFACE AC CHARACTERISTICS 224 18 3 MISC PIN AC CHARACTERISTICS 225 18 4 OVERHEAD PORT AC CHARACTERISTI...

Page 8: ...Interface Pin Timing 41 Figure 8 15 E3 G 832 SCT Mode Transmit Serial Interface Pin Timing 41 Figure 8 16 DS3 SCT Mode Receive Serial Interface Pin Timing 42 Figure 8 17 E3 G 751 SCT Mode Receive Seri...

Page 9: ...iagram 210 Figure 13 2 JTAG TAP Controller State Machine 211 Figure 13 3 JTAG Functional Timing 214 Figure 14 1 DS3174 Pin Assignments 400 Lead PBGA 215 Figure 14 2 DS3173 Pin Assignments 400 Lead PBG...

Page 10: ...larm Monitor Select 67 Table 10 17 Loopback Mode Selections 69 Table 10 18 Line AIS Enable Modes 73 Table 10 19 Payload Downstream AIS Enable Modes 74 Table 10 20 TSOFIn Input Pin Functions 75 Table 1...

Page 11: ...Register Map 195 Table 12 28 Receive G 832 E3 Framer Register Map 198 Table 12 29 Transmit Clear Channel Register Map 207 Table 12 30 Receive Clear Channel Register Map 208 Table 13 1 JTAG Instruction...

Page 12: ...IAD Figure 2 1 shows an application for the DS3174 Figure 2 1 Four Port DS3 E3 Line Card Digital Cross Connect DCS DS3174 Quad DS3 E3 SCT T3 E3 Trans formers Four DS3 E3 Lines DS3 E 3 Backplane Signal...

Page 13: ...Loss of Signal LOS detectors ANSI T1 231 and ITU G 775 Per channel power down control 3 3 Receive DS3 E3 Framer Features Frame synchronization for M23 or C bit Parity DS3 or G 751 E3 or G 832 E3 B3ZS...

Page 14: ...put reference clock Input reference clock can be 51 84 MHz 44 736MHz or 34 368 MHz Internally derived clocks can be used as references for LIU and jitter attenuator Derived clocks can be transmitted o...

Page 15: ...ALB transmit to receive Line facility loopback LLB receive to transmit with optional transmission of unframed all one AIS payload toward system trunk interface Framer diagnostic loopback DLB transmit...

Page 16: ...structure Fifth Edition 1993 ITU T G 703 Physical Electrical Characteristics of Hierarchical Digital Interfaces 1991 G 704 Synchronous Frame Structures Used at 1544 6312 2048 8488 and 44 736 kbit s Hi...

Page 17: ...Mode CLAD Clock Rate Adapter Clear Channel A Datastream with no framing included also known as Unframed FRM Frame Mode FSCT Framer Single Chip Transceiver Mode HDLC High Level Data Link Control Packe...

Page 18: ...ifferent operational modes The line interface operational mode is determined by the LM 2 0 bits 6 1 DS3 E3 SCT Mode This mode is for standard operation that uses the device in the single chip transcei...

Page 19: ...AP DS3 E3 Transmit LIU IEEE P1149 1 JTAG Test Access Port JTDO JTCLK JTMS JTDI JTRST HDLC FEAC LLB DLB DS3 E3 Transmit Formatter DS3 E3 Receive Framer Trail Trace Buffer ROHn ROHCLKn ROHSOFn TCLKIn RS...

Page 20: ...n RXNn TPOSn TDATn TNEGn TLCLKn Microprocessor Interface TXPn TXNn RDATn RNEGn RLCVn RST n port 1 4 D 15 0 A 10 1 ALE CS RD DS WR R W MODE INT GPIO 8 1 WIDTH RDY A 0 BSWAP DS3 E3 Transmit LIU IEEE P11...

Page 21: ...RZCDS bits in the line encoder decoder block select between no encoding decoding AMI and encoding decoding B3ZS HDB3 When the HDB3 B3ZS line decoder encoder is enabled the framing modes FM bits select...

Page 22: ...3ZS AMI LIU Mode n port 1 4 RXPn RXNn TXPn TXNn LLB DLB DS3 E3 Receive LIU TAIS TUA1 Clock Rate Adapter CLKA CLKB CLKC ALB B3ZS HDB3 Encoder B3ZS HDB3 Decoder FROM FRAMING LOGIC OR EXTERNAL PINS TO FR...

Page 23: ...onfiguration selected by the FM bits The DS3 modes select the B3ZS line code while the E3 modes select the HDB3 line code Table 7 2 HDB3 B3ZS AMI Non LIU Mode Configuration Registers MODE LM 2 0 LINE...

Page 24: ...coder block is disabled except for the BPV counter which is used to count RLCV errors Table 7 3 UNI Line Interface Mode Configuration Registers MODE LM 2 0 LINE TCR TZSD LINE RCR RZSD TLEN PORT CR2 Un...

Page 25: ...A12 W8 B8 RXPn Ia Receive Positive analog W5 B5 R2 F2 RXNn Ia Receive Negative analog Y5 A5 R1 F1 RPOSn RDATn Ia Positive AMI Data W15 B15 Y3 A3 RNEGn RLCVn Ia Negative AMI Line Code Violation Y15 A1...

Page 26: ...be active low Data Strobe active low K3 WR R W I Write Strobe active low R W Select K4 RDY Oz Ready handshake active low K2 INT Oz Interrupt active low L4 MODE I Mode select RD WR or DS strobe mode B1...

Page 27: ...PWR Digital 3 3V H8 H7 H6 G8 G7 G6 F8 F7 F6 A2 R8 R7 R6 P8 P7 P6 N8 N7 N6 W1 R15 R14 R13 P15 P14 P13 N15 N14 N13 Y19 H15 H14 H13 G15 G14 G13 F15 F14 F13 B20 AVDDRn PWR Analog 3 3V for receive LIU on...

Page 28: ...s pin The signal is updated on the positive clock edge of the referenced clock pin if the clock pin signal is not inverted otherwise it is updated on the falling edge of the clock The signal is typica...

Page 29: ...RLCLKn line clock input pins but it can be referenced to the RCLKOn output pins This input signal can be inverted RDATn When the port line interface is configured for UNI mode the un encoded receive...

Page 30: ...s In T3 mode the first X bit is marked In G 751 E3 mode the first bit of the FAS word is marked In G 832 E3 mode the first bit of the FA1 byte is marked The sequence starts on the same high to low tra...

Page 31: ...ansmit Serial Data TSERn When the port framer is configured for either the DS3 or E3 SCT modes this pin is used as the source of the DS3 E3 payload data When the port is configured for a clear channel...

Page 32: ...erted o DS3 44 736 Mbps 20ppm o E3 34 368 Mbps 20ppm RCLKOn RGCLKn O Receive Clock Output Gapped Clock See Table 10 24 RCLKOn When the port framer is configured for the DS3 or E3 framed modes and RCLK...

Page 33: ...the signal goes back high ALE should be tied high for non multiplexed address systems CS I Chip Select active low CS This signal must be low during all accesses to the registers RD DS I Read Strobe ac...

Page 34: ...gnal enables the internal scan test mode when low For normal operation tie high This is an asynchronous input HIZ I High impedance test enable active low HIZ This signal puts all digital output and bi...

Page 35: ...is pin is a STS 1 51 84 MHz 20ppm input signal when the CLAD is disabled or it can be enabled to output a generated clock when the CLAD is enabled The pin is driven low when it is not selected to outp...

Page 36: ...ted otherwise they change after the negative edge The TLCLKn clock pin is the clock reference typically used for the TPOSn and TNEGn signals but they can be time referenced to the TCLKIn TCLKOn RLCLKn...

Page 37: ...at the rising edge of the reference clock signal if the clock pin is not inverted otherwise they are sampled at the negative edge The RLCLKn clock pin is the clock reference used for the RPOSn and RN...

Page 38: ...KOn RLCLKn or RCLKOn clock pins The TDATn pins can be inverted See Figure 8 5 Figure 8 5 TX Line IO UNI Functional Timing Diagram 8 3 1 4 UNI Mode Receive Pin Functional Timing The RDATn pin is availa...

Page 39: ...AS 10 FAS 9 Figure 8 8 shows the relationship between the E3 G 751 receive overhead port pins Figure 8 8 E3 G 751 Framing Receive Overhead Port Timing ROH ROHSOF ROHCLK N A FAS 10 1 2 3 4 5 6 7 8 9 10...

Page 40: ...7 18 19 20 21 22 23 24 15 FA1 2 FA1 3 FA1 1 FA1 6 FA1 5 FA1 4 FA1 7 FA1 8 FA2 2 FA2 3 FA2 1 FA2 6 FA2 5 FA2 4 FA2 7 FA2 8 EM 2 EM 3 EM 1 EM 5 EM 4 TOHSOF TOHEN 8 3 3 DS3 E3 Serial Data Interface 8 3 3...

Page 41: ...SER DATA IS OVERWRITTEN WITH OH TSOFI 6 7 8 9 10 11 12 13 1 2 3 4 5 14 15 16 17 18 19 20 8 3 3 2 DS3 E3 SCT Mode Receive Serial Interface Pin Functional Timing The RSERn signal has the DS3 or E3 paylo...

Page 42: ...G 832 SCT Mode Receive Serial Interface Pin Timing E3 RSER E3 RDEN E3 RGCLK FA1 11110110 RCLKO or RCLKI RSOF FA2 00101000 6 7 8 9 10 11 12 13 1 2 3 4 5 14 15 16 17 18 19 20 8 3 4 Microprocessor Interf...

Page 43: ...74 43 Figure 8 19 16 Bit Mode Write 0x1234 0x2B0 D 15 0 A 10 1 RD WR CS A 0 BSWAP RDY Z Z Note Address 0x2B0 0x1234 Figure 8 20 16 Bit Mode Read D 15 0 A 10 1 A 0 BSWAP 0x2B0 0x1234 Z Z Note Address 0...

Page 44: ...0x2B0 0x34 Z Z 0x2B0 0x12 Z Z Note Address 0x2B0 0x34 0x2B1 012 RD WR CS RDY Figure 8 23 and Figure 8 24 are examples of databuses without and with byte swapping enabled respectively When the A 0 BSWA...

Page 45: ...bits in the register while the clear on write clears only those bits which are written with a 1 when the user writes to the status latched register To use the Clear on Read method the user must only r...

Page 46: ...BSWAP 0x1C0 0xFFFF 0x1C0 0x5555 0x1C0 0xAAAA Z Z Z Z Z Z RD WR CS RDY Figure 8 27 and Figure 8 28show exaggerated views of the Ready Signal to describe the difference in access times to write or read...

Page 47: ...ite 0x1234 0x0078 0x2B0 0x3A4 D 15 0 A 10 1 A 0 BSWAP Z Z Z Z RD WR CS RDY Figure 8 28 RDY Signal Functional Timing Read D 15 0 A 10 1 A 0 BSWAP 0x1C0 0xFFFF 0x3A4 0xFFFF Z Z Z Z RD WR CS RDY See also...

Page 48: ...or default mode Default mode Framer C bit DS3 LIU Disabled STEP 4 Clear the Data Path Resets and the Port Power Down bit The default value of the Data Path Resets is one which keeps the internal logic...

Page 49: ...f the incoming signal Verify that the CLAD is configured to match the clock input on the CLKA CLKB and CLKC pins DS3 E3 STS 1 See Table 10 11 Loss of Signal LINE RSR LOS This indicates that the LIU is...

Page 50: ...data bus lines D 7 0 When the A 0 BSWAP pin is high the upper register bits REG 15 8 are mapped to the lower external data bus lines D 7 0 and the lower register bits REG 7 0 are mapped to the upper e...

Page 51: ...the interrupt pin 10 1 8 Interrupt Structure The interrupt structure is designed to efficiently guide the user to the source of an enabled interrupt source The status bits in the global status GL SR...

Page 52: ...ive the INT pin low when a particular status bit gets set For example in order to enable DS3 Out of Frame interrupts on Port 2 the following registers would need to be written Register bit Address Val...

Page 53: ...f TLCLKn is used as the timing source be sure to set PORT CR3 TLTS 0 for output timing When PLB is enabled the TCLKIn pin will not be used and the internal transmit clock is switched to the internal r...

Page 54: ...d in the port configuration registers LIUEN is not a register bit it is a variable based on the line mode bits Table 10 1 decodes the LM bits for LiUEN selection Table 10 1 LIU Enable Table LM 2 0 LIU...

Page 55: ...11 PLB 1 X RX LIU 0 011 PLB 0 X RLCLKn 0 000 NO X 0 CLAD 0 001 NO X 0 CLAD 0 100 NO X 0 CLAD 0 10X NO X 0 CLAD 0 111 NO X 0 CLAD 0 000 NO X 1 TCLKIn 0 001 NO X 1 TCLKIn 0 100 NO X 1 TCLKIn 0 10X NO X...

Page 56: ...KOn signals Figure 10 3 Internal RX Clock 0 1 0 1 Rx LIU CLOCK RLCLK LIUEN TCLKO DIAGNOSTIC LOOPBACK RCLKO Table 10 5 identifies the source of the output signal RCLKOn based on certain variables and r...

Page 57: ...e Signal Pin Valid Timing Source Select LOOPT LBM 2 0 LIUEN CLADC TLTS Valid Timing to These Clock Pins 1 XXX X X 0 TLCLKn TCLKOn RCLKOn 1 XXX 0 X 1 RLCLKn 1 XXX 1 X 1 No valid timing to any input clo...

Page 58: ...erface Pin Signal Timing Source Select LOOPT LBM 2 0 LIUEN CLADC Valid Timing to These Clock Pins X XXX 0 X RLCLKn X XXX 1 X No valid timing to any clock pin 10 2 3 4 Receiver Framer Pin Timing Source...

Page 59: ...y of the clock pins for setup hold timing on clock input and output pins There will be a flop at each input whose clock is connected to the signal from the input or output clock source pins with as li...

Page 60: ...pending on which mode the device is configured for In the internal DS3 or E3 frame modes the transmit gapped clock is created by the logical OR of the TCLKOn and TDENn signals creating a positive or n...

Page 61: ...everything including the control register bits excluding the reset bit All clocks are functional being controlled by configuration bits while data path reset is active The LIU and CLAD circuits will...

Page 62: ...odes then clear the GL CR1 RSTDP and PORT CR1 RSTDP bits This would cause the logic in the ports to start up in a repeatable sequence The device can also be initialized by clearing the GL CR1 RSTDP PO...

Page 63: ...d upon the mode the user selects via the FM bits The CLAD output is also available as a transmit clock source if selected via the PORT CR2 CLADC register bit The user must supply at least one of the t...

Page 64: ...nput Low output Low output 11 01 STS 1 clock input E3 output Low output 11 10 STS 1 clock input Low output DS3 clock output 11 11 STS 1 clock input DS3 clock output E3 clock output 10 4 2 8 kHz Refere...

Page 65: ...101 Port 2 8KREF source selected by P8KRS 1 0 0 110 Port 3 8KREF source selected by P8KRS 1 0 0 111 Port 4 8KREF source selected by P8KRS 1 0 1 XXX GPIO4 pin Table 10 13 lists the selectable sources...

Page 66: ...grammed as global input or output signals When the device is bonded out or has ports powered down to have 1 2 or 3 ports active the GPIO pins associated with the disabled ports will still operate as e...

Page 67: ...one so that that event will be counted The Performance Monitor Update signal affects the counter registers of the following blocks the BERT the DS3 E3 framer the Line Encoder Decoder The update clear...

Page 68: ...g the global GL CR1 TMEI bit using the port PORT CR1 TMEI bit or by using the GPIO6 pin configured for TMEI mode There is a transmit error insertion register in the functional blocks that allow error...

Page 69: ...insertion bit 0 1 T3 ERROR INSERT 10 5 Per Port Resources 10 5 1 Loopbacks There are several loop back paths available The following table lists the loopback modes available for analog loopback ALB l...

Page 70: ...3 Decoder 10 5 1 1 Analog Loopback ALB Analog loopback is enabled by setting PORT CR4 LBM 2 0 001 Analog loopback mode will not be enabled when the port is configured for loop timed mode set via the P...

Page 71: ...still be enabled using PORT CR1 LAIS 2 0 even when DLB is enabled Refer to Figure 10 10 10 5 2 Loss Of Signal Propagation The Loss Of Signal LOS is detected in the line decoder logic In unipolar UNI l...

Page 72: ...ill be looped back to the receive side when DLB is activated The receive framer can detect both unframed all ones AIS and DS3 framed AIS patterns When in DS3 framing modes both framed DS3 AIS and unfr...

Page 73: ...RAMER TAIS DAIS TAIS DAIS TRANSMIT LINE RECEIVE LINE TRANSMIT PAYLOAD RECEIVE PAYLOAD TSOFO LINE TRIBUTARY SIDE SYSTEM TRUNK SIDE Table 10 18 lists the LAIS decodes for various line AIS enable modes T...

Page 74: ...cket instead of allowing a bad and possibly very long HDLC packet 10 5 6 Trail Trace There is a single Trail Trace controller for use in line maintenance protocols The E3 G 832 framer has access to th...

Page 75: ...0XX FSCT 1 TCLKOn none 1XX FBM X TCLKOn none 10 5 8 2 Receive SCT port pins The receive SCT pins are RSERn RSOFOn RDENn and RCLKOn RGCLKn They have different functions based on the framing mode and ot...

Page 76: ...2 0 control bits The major blocks controlled are the transmit LIU TX LIU receive LIU RX LIU jitter attenuator JA and the line encoder decoder The line encoder decoder is used for B3ZS HDB3 and AMI lin...

Page 77: ...elect Bits LM 2 0 LINE TCR TZSD LINE RCR RZSD LM 2 0 PORT CR2 Line Code LIU JA 0 000 B3ZS HDB3 OFF OFF 0 001 B3ZS HDB3 ON OFF 0 010 B3ZS HDB3 ON TX 0 011 B3ZS HDB3 ON RX 1 000 AMI OFF OFF 1 001 AMI ON...

Page 78: ...FEAC LLB DLB DS3 E3 Transmit Formatter DS3 E3 Receive Framer Trail Trace Buffer DS3 E3 Receive LIU TAIS TUA1 Clock Rate Adapter TX BERT RX BERT PLB ALB UA1 GEN B3ZS HDB3 Encoder B3ZS HDB3 Decoder 10...

Page 79: ...E3 data stream performing framing performance monitoring overhead extraction and generates downstream AIS if necessary The bits in a byte are received MSB first LSB last When they are output serially...

Page 80: ...n All four bit positions must fail before any other bit positions are checked for a subframe boundary There are 170 possible bit positions that must be checked and four positions are checked simultane...

Page 81: ...UA1 and RDI The errors accumulated are framing P bit parity C bit parity C bit format only and Far End Block Error FEBE C bit format only errors An Out Of MultiFrame OOMF condition is declared when a...

Page 82: ...cutive 2047 bit windows five or less zeros are detected and an OOF condition is continuously present A RUA1 condition is terminated if in each of 4 consecutive 2047 bit windows six or more zeros are d...

Page 83: ...lly programmable on or off The Application Identification Channel AIC is stored in a register bit It is determined from the C11 bit The AIC is set to one C bit format if the C11 bit is set to one in t...

Page 84: ...bit generation is enabled or frame generation is enabled The bits C11 C12 C21 C22 C23 C61 C62 C63 C71 C72 and C73 are all overwritten with a one The bit C13 is overwritten with the Far End Alarm and C...

Page 85: ...and FX4 bits are overwritten with the values one zero zero and one 1001 respectively X1 and X2 are overwritten with 11 And P1 P2 C31 C32 and C33 are overwritten with the calculated payload parity from...

Page 86: ...ero zero and one 1001 respectively The X bits X1 and X2 are both overwritten with the Remote Defect Indicator RDI The RDI source is programmable automatic 1 or 0 If the RDI is generated automatically...

Page 87: ...transmit overhead data enable signal TOHEN is driven high then the bit on the transmit overhead signal TOH is inserted into the output data stream Insertion of bits using the TOH signal overwrites int...

Page 88: ...ndication A bit The A bit can be generated automatically sourced from the transmit FEAC controller set to one or set to zero The A bit source is programmable automatic FEAC 1 or 0 If the A bit is gene...

Page 89: ...OOF condition has been detected The use of an off line framer reduces the average time required to reframe and reduces data loss caused by burst error The G 751 E3 framer checks each bit position for...

Page 90: ...tting the receive alarm indication on LOS OOF LOF or AIS is individually programmable on or off 10 6 7 6 3 Receive G 751 E3 Overhead Extraction Overhead extraction extracts all of the E3 overhead bits...

Page 91: ...Signal Label MI Multi frame Indicator TM Timing Marker RDI REI SL SL SL MI MI TM MSB 1 LSB 8 Table 10 29 shows the function of each overhead bit in the DS3 frame Table 10 29 G 832 E3 Frame Overhead B...

Page 92: ...MA byte in each frame The multiframe indicator and timing marker bits can be directly inserted from a 3 bit register or generated from a 4 bit register The multiframe indicator and timing marker inser...

Page 93: ...sertion 10 6 8 5 Transmit G 832 E3 AIS Generation G 832 E3 AIS generation overwrites the data stream with AIS If transmit AIS is enabled the data stream payload and E3 overhead is forced to all ones 1...

Page 94: ...dition is first detected A bit error increments the count once for each bit in FA1 and each bit in FA2 that does not match its expected value up to 16 per frame A byte error increments the count once...

Page 95: ...the timing source indicator bit indicated by the multiframe indicator bits first second third or fourth bit respectively The four timing source indicator bits are extracted from the multiframe integr...

Page 96: ...d bit 7 This is to differentiate between a byte in a register and the corresponding byte in a signal See Figure 10 20 for the location of HDLC controllers within the DS317x devices Figure 10 20 HDLC C...

Page 97: ...disabled the outgoing 8 bit data stream DT 1 8 with DT 1 being the MSB and DT 8 being the LSB is input from the Transmit FIFO with the MSB in TFD 0 and the LSB in TFD 7 of the transmit FIFO data TFD 7...

Page 98: ...ontiguous 1 s After destuffing is completed the serial bit stream is demultiplexed into an 8 bit parallel data stream and passed on with packet start packet end and packet abort indications If there i...

Page 99: ...for transmit one for receive The Trail Trace Controller demaps a 16 byte trail trace identifier from the E3 G 832 TR Byte of the overhead in the receive direction and maps a trace identifier into the...

Page 100: ...f the transmit trail path trace identifier memory will be random data immediately after power up and will not change during a reset RST or DRST low 10 8 5 Transmit Trace ID Processor The Transmit Trac...

Page 101: ...utive times An Idle condition is terminated when a non zero trail trace identifier is received five consecutive times or a TIU condition is declared A TIU condition is declared if eight consecutive tr...

Page 102: ...g See Figure 10 23 for the location of the FEAC Controller in the block diagram Figure 10 23 FEAC Controller Block Diagram DS3 E3 Transmit LIU IEEE P1149 1 JTAG Test Access Port Microprocessor Interfa...

Page 103: ...4 C3 C2 C1 FEAC code extraction determines the codeword boundary by identifying the codeword sequence and extracts the FEAC code A FEAC codeword is a repeating 16 bit pattern See Figure 10 24 The code...

Page 104: ...o an AMI bipolar signal POS data and NEG data and vice versa Programmable zero suppression B3ZS or HDB3 zero suppression encoding and decoding can be performed or the bipolar data stream can be left a...

Page 105: ...pulse data TPOSn and negative pulse data TNEGn TPOSn and TNEGn are updated on the rising edge of TLCLKn 10 10 5 Receive Line Interface The Receive Line Interface receives a bipolar signal The incoming...

Page 106: ...r bipolar violation BPV errors and E3 code violation CV errors A BPV error is declared if two 1 s are detected on RXP or RXN without an intervening 1 on RXN or RXP and the 1 s are not part of a B3ZS H...

Page 107: ...Block within the DS3174x devices Figure 10 28 BERT Block Diagram DS3 E3 Transmit LIU IEEE P1149 1 JTAG Test Access Port Microprocessor Interface HDLC FEAC LLB DLB DS3 E3 Transmit Formatter DS3 E3 Rece...

Page 108: ...pattern which will occur when it receives a minimum 6 bit errors within a 64 bit window The Receive BERT Bit Count Register BERT RBCR1 and the Receive BERT Bit Error Count Register BERT RBECR1 will be...

Page 109: ...am Figure 10 29 PRBS Synchronization State Diagram Sync Load Verify 1 bit error 32 bits loaded 3 2 b i t s w i t h o u t e r r o r s 6 o f 6 4 b i t s w i t h e r r o r s 10 11 4 2 Receive Repetitive...

Page 110: ...bit LSB or bit 1 to the most significant bit MSB or bit 32 The input to bit 1 is the feedback For a PRBS pattern generating polynomial xn xy 1 the feedback is an XOR of bit n and bit y For a repetitiv...

Page 111: ...Clock Data Recovery and Transmit Waveshaping Jitter Attenuators can be Placed in Either the Receive or Transmit Paths Interface to 75 Coaxial Cable at Lengths Up to 380 meters DS3 440 meters E3 Use 1...

Page 112: ...B3ZS HDB3 ENCODER FROM DS3 E3 LINE TO DS3 E3 LINE 10 12 4 Transmitter 10 12 4 1 Transmit Clock The clock used in the LIU Transmitter is typically based on either the CLAD clock or TCLKI selected by t...

Page 113: ...are put in a high impedance state and the transmit amplifiers are powered down 10 12 4 6 Transmitter Jitter Generation Intrinsic The transmitter meets the jitter generation requirements of all applica...

Page 114: ...signal of nominal amplitude and pulse shape to the clock and data recovery block The AGC equalizer block automatically handles direct 0 meters monitoring of the transmitter output signal 10 12 5 4 Cl...

Page 115: ...the CDR block 18dB is in the tolerance range of G 775 where LOS may or may not be declared 10 12 5 6Receiver Power Down To minimize power consumption when the receiver is not being used write a one to...

Page 116: ...tched on change bit is a latched bit that is set when the event occurs and when it goes away A latched status bit can be cleared using clear on read or clear on write techniques selectable by the GL C...

Page 117: ...nd reserved registers The following table is a map of the registers for each port The address offset is from the start of each port range of 000h 200h 400h and 600h In a DS3183 writes to registers in...

Page 118: ...t common registers 060 07F BERT 080 08B Reserved 08C 08F B3ZS HDB3 transmit line encoder 090 09F B3ZS HDB3 receive line decoder 0A0 0AF HDLC Transmit 0B0 0BF HDLC Receive 0C0 0CF FEAC Transmit 0D0 0DF...

Page 119: ...bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 000 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 000 001 GL IDR R ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 002 TMEI MEIMS GPM1 GPM0 PMU LSBCRE RSTDP RST 002...

Page 120: ...RES TSOFOI RES TSERI TOHSI TOHEI J4C ROHI ROHCKI RNEGI RPOSI RLCKI RCLKOI J4C J4D PORT INV2 RW RES RES RSOFOI RSERI ROHSI J4E J4E J4F UNUSED J50 TTSR FSR HSR BSR RES RES RES FMSR J50 J51 PORT ISR R PS...

Page 121: ...20 BC19 BC18 BC17 BC16 J7A J7B BERT RBCR2 R BC31 BC30 BC29 BC28 BC27 BC26 BC25 BC24 J7C J7C J7E J7F UNUSED Table 12 4 Line Register Bit Map Address Register Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bi...

Page 122: ...UNUSED JB0 RBRE RDIE RFPD RFRST JB0 JB1 HDLC RCR RW RDAL4 RDAL3 RDAL2 RDAL1 RDAL0 JB2 JB2 JB3 UNUSED JB4 RFF RFE RHDA JB4 JB5 HDLC RSR R JB6 RFOL RPEL RPSL RFFL RHDAL JB6 JB7 HDLC RSRL RL JB8 RFOIE R...

Page 123: ...Bit 0 16 bit 8 bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 JE8 Reserved TMAD TIDLE TDIE TBRE JE8 JE9 TT TCR RW JEA Reserved Reserved TTIA3 TTIA2 TTIA1 TTIA0 JEA JEB TT TTIAR R JEC TTD7...

Page 124: ...LOFIE RAIIE AISIE OOFIE LOSIE K2C K2D T3 RSRIE1 RW Reserved Reserved Reserved Reserved T3FMIE AICIE IDLEIE RUA1IE K2E CPECIE FBECIE PECIE FECIE K2E K2F T3 RSRIE2 RW CPEIE FBEIE PEIE FEIE K30 K30 K32...

Page 125: ...RVED K34 FE7 FE6 FE5 FE4 FE3 FE2 FE1 FE0 K34 K35 E3G751 RFECR R FE15 FE14 FE13 FE12 FE11 FE10 FE9 FE8 K36 K36 K3A K3B RESERVED K3C K3C K3E K3F UNUSED 12 1 5 E3 G 832 Register Bit Map Table 12 10 E3 G...

Page 126: ...1 6 Clear Channel Register Bit Map Table 12 11 Clear Channel Register Bit Map Address Register Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 16 bit 8 bit Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit...

Page 127: ...vice CODE ID Bits 11 to 0 ID11 to ID0 These bits of the device code ID register has same information as the lower 12 bits of JTAG CODE ID portion of the JTAG ID register JTAG ID 23 12 Address Register...

Page 128: ...TMEI bit 1 Global error insertion using the GPIO6 pin Bits 5 and 4 Global Performance Monitor Update Mode GPM 1 0 These bits select the global performance monitor register update mode 00 Global PM upd...

Page 129: ...ce The source is selected from one of the CLAD clocks or from one of the port 8KREF clock sources These bits are ignored when the G8KIS bit 1 See Table 10 12 Bit 9 Global 8KHz Reference Output Select...

Page 130: ...e GPIO6 pin These selections are only valid if GL CR1 MEIMS 0 00 Input 01 Port 3 B status output selected by PORT CR4 GPIOB 3 0 in port control registers 10 Output logic 0 11 Output logic 1 Bits 9 to...

Page 131: ...This bit is set when any of the latched status register bits in the global latched status register GL SRL are set and enabled for interrupt The INT interrupt pin will be driven low when this bit is s...

Page 132: ...SL Bit 4 8K Reference Activity Status Latched 8KREFL This bit will be set when the 8 kHz reference signal on the GPIO4 pin is active The GL CR2 G8KIS bit must be set for the activity to be monitored B...

Page 133: ...errupt pin will be driven when this bit is enabled the GL SRL CLOLL is set and GL ISRIE GSRIE bit is enabled 0 interrupt disabled 1 interrupt enabled Bit 0 Global Performance Monitoring Update Status...

Page 134: ...l Register 3 0 2 4 6 46h PORT CR4 Port Control Register 4 0 2 4 6 48h Unused 0 2 4 6 4Ah PORT INV1 Port IO Invert Control Register 1 0 2 4 6 4Ch PORT INV2 Port IO Invert Control Register 2 0 2 4 6 4Eh...

Page 135: ...d by the GL CR1 MEIMS bit 0 Port software update via PORT CR1 TMEI 1 Global update source Bit 4 Performance Monitor Update Mode PMUM These bits select the method of updating the performance monitor re...

Page 136: ...has no effect when the LIU is disabled and powered down 0 TXPn and TXNn driven 1 TXPn and TXNn tri stated Bit 13 Receive LIU Monitor Mode RMON This bit is used to enable the receive LIU monitor mode p...

Page 137: ...selects the source of the 8 kHz reference from the port sources The 8K reference for this port can also be used as the global 8K reference source 0 Selects the receive internal framer clock based on R...

Page 138: ...0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name GPIOB3 GPIOB2 GPIOB1 GPIOB0 GPIOA3 GPIOA2 GPIOA1 GPIOA0 Default 0 0 0 0 0 0 0 0 Bits 10 to 8 Loopback Mode 2 0 LBM 2 0 These bits select the loopback modes for a...

Page 139: ...n set Bit 9 TOHSOFn Invert TOHSI This bit inverts the TOHSOFn pin when set Bit 8 TOHENn Invert TOHEI This bit inverts the TOHENn pin when set Bit 7 TOHn Invert TOHI This bit inverts the TOHn pin when...

Page 140: ...ENn pin when set Bit 10 RSERn Invert RSERI This bit inverts the RSERn pin when set Bit 9 ROHSOFn Invert ROHSI This bit inverts the ROHSOFn pin when set Bit 7 ROHn Invert ROHI This bit inverts the ROHn...

Page 141: ...set The interrupt pin will be driven when this bit is set and the corresponding GL ISRIE PISRIE 4 1 is set Bit 6 FEAC Status Register Interrupt Status FSR This bit is set when any of the latched statu...

Page 142: ...cates the status of the receive LIU clock recovery PLL circuit 0 Locked to the incoming signal 1 Not locked to the incoming signal Bit 0 Performance Monitoring Update Status PMS This bits indicates th...

Page 143: ...SRIE RLOLIE bit is set and the corresponding GL ISRIE PISRIE 4 1 bit is also set Bit 0 Performance Monitoring Update Status Latched PMSL This bit will be set when the PORT SR PMS status bit changes f...

Page 144: ...6 7Ch Unused 0 2 4 6 7Eh Unused 12 4 2 BERT Register Bit Descriptions Register Name BERT CR Register Description BERT Control Register Register Address 0 2 4 6 60h Bit 15 14 13 12 11 10 9 8 Name Defa...

Page 145: ...o zero and back to one for another resynchronization to be initiated Note A manual resynchronization forces the receive pattern generator out of the Sync state Bit 2 Automatic Pattern Resynchronizatio...

Page 146: ...orced to a PRBS pattern with a generating polynomial of x20 x17 1 The output of the pattern generator will be forced to one if the next fourteen output bits are all zero Bit 5 Pattern Type Select PTS...

Page 147: ...P20 BSP19 BSP18 BSP17 BSP16 Default 0 0 0 0 0 0 0 0 Bits 15 to 0 BERT Seed Pattern BSP 31 16 Upper 16 bits of 32 bits BERT Seed Pattern BSP 31 0 These 32 bits are the programmable seed for a transmit...

Page 148: ...rror rate will be started after the next error is inserted TEIR 2 0 Error Rate 000 Disabled 001 1 x 10 1 010 1 x 10 2 011 1 x 10 3 100 1 x 10 4 101 1 x 10 5 110 1 x 10 6 111 1 x 10 7 Bit 2 Bit Error I...

Page 149: ...is cleared when the user updates the BERT counters via the PMU bit BERT CR Bit 0 Out Of Synchronization OOS When 0 the receive pattern generator is synchronized to the incoming pattern When 1 the rece...

Page 150: ...Bit Error Count Interrupt Enable BECIE This bit enables an interrupt if the BECL bit is set and the bit in GL ISRIE PSRIE 4 1 that corresponds to this port is set 0 interrupt disabled 1 interrupt ena...

Page 151: ...ster 1 Register Address 0 2 4 6 78h Bit 15 14 13 12 11 10 9 8 Name BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Default 0 0 0...

Page 152: ...only AMI encoding is performed Bit 3 Excessive Zero Insert Enable EXZI When 0 excessive zero EXZ event insertion is disabled When 1 EXZ event insertion is enabled Bit 2 Bipolar Violation Insert Enable...

Page 153: ...ture if a zero is followed by a bipolar violation BPV and an HDB3 signature if two zeros are followed by a BPV When 1 BPV error detection detects a B3ZS signature if a zero is followed by a BPV that h...

Page 154: ...n a loss of signal LOS condition When 1 the receive line is in an LOS condition See Section 10 10 6 Note When zero suppression B3ZS or HDB3 decoding is disabled the LOS condition is cleared and cannot...

Page 155: ...abled 1 interrupt enabled Bit 3 Excessive Zero Count Interrupt Enable EXZCIE This bit enables an interrupt if the LINE RSRL EXZCL bit is set and the bit in GL ISRIE PSRIE 4 1 that corresponds to this...

Page 156: ...lations detected on the incoming bipolar data stream This register is updated via the PMU signal see Section 10 4 5 Register Name LINE REXZCR Register Description Line Receive Excessive Zero Count Reg...

Page 157: ...ate the minimum number of bytes TDAL x 8 1 that must be available for storage do not contain data in the Transmit FIFO for HDLC data storage to be available For example a value of 21 15h results in HD...

Page 158: ...ompleted When 1 the Transmit FIFO is emptied any transfer in progress is halted the FIFO RAM is powered down and all incoming data is discarded all TFDR register writes are ignored Register Name HDLC...

Page 159: ...than the Transmit HDLC data storage available level TDAL 4 0 When 1 the Transmit FIFO has the same or more storage space available than the Transmit FIFO HDLC data storage available level Register Na...

Page 160: ...disabled 1 interrupt enabled Bit 3 Transmit Packet End Interrupt Enable TPEIE This bit enables an interrupt if the TPEL bit is set and the bit in GL ISRIE PSRIE 4 1 that corresponds to this port is se...

Page 161: ...in data in the Receive FIFO before HDLC data is considered to be available RHDA 1 For example a value of 21 15h results in HDLC data being available when the Receive FIFO contains 168 A8h bytes or mor...

Page 162: ...e or more data than the Receive HDLC data available level Register Name HDLC RSRL Register Description HDLC Receive Status Register Latched Register Address 0 2 4 6 B6h Bit 15 14 13 12 11 10 9 8 Name...

Page 163: ...the RPEL bit is set and the bit in GL ISRIE PSRIE 4 1 that corresponds to this port is set 0 interrupt disabled 1 interrupt enabled Bit 3 Receive Packet Start Interrupt Enable RPSIE This bit enables...

Page 164: ...to 8 Receive FIFO Data RFD 7 0 These eight bits are the packet data stored in the Receive FIFO RFD 7 is the MSB and RFD 0 is the LSB If bit reordering is disabled RFD 0 is the first bit received and R...

Page 165: ...4 6 C0h Bit 15 14 13 12 11 10 9 8 Name Default 0 0 0 0 1 0 0 0 Bit 7 6 5 4 3 2 1 0 Name TFCL TFS1 TFS0 Default 0 0 0 0 0 0 0 0 Bit 2 Transmit FEAC Codeword Load TFCL A 0 to 1 transition on this bit lo...

Page 166: ...mit FEAC code A data to be stored inserted into codeword A TFCA 5 is the LSB last bit transmitted of the FEAC code C 6 and TFCA 0 is the MSB first bit transmitted of the FEAC code C 1 Register Name FE...

Page 167: ...2 4 6 D0h FEAC RCR FEAC Receive Control Register 0 2 4 6 D2h Unused 0 2 4 6 D4h FEAC RSR FEAC Receive Status Register 0 2 4 6 D6h FEAC RSRL FEAC Receive Status Register Latched 0 2 4 6 D8h FEAC RSRIE...

Page 168: ...en 0 the Receive FEAC processor is not receiving a FEAC Idle signal all ones When 1 the Receive FEAC processor is receiving a FEAC Idle signal Register Name FEAC RSRL Register Description FEAC Receive...

Page 169: ...enabled Bit 0 Receive FEAC Idle Interrupt Enable RFIIE This bit enables an interrupt if the RFIL bit is set and the bit in GL ISRIE PSRIE 4 1 that corresponds to this port is set 0 interrupt disabled...

Page 170: ...Transmit Multi frame Alignment Insertion Disable TMAD When 0 multi frame alignment signal MAS insertion is enabled and the first bit transmitted of each trail trace byte is overwritten with an MAS bit...

Page 171: ...trace identifier Note The value of these bits increments with each transmit trail trace identifier memory access when these bits are Fh a memory access will return them to 0h Register Name TT TIR Reg...

Page 172: ...10 9 8 Name Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved RMAD RETCE RDIE RBRE Default 0 0 0 0 0 0 0 0 Bit 3 Receive Multi frame Alignment Disable RMAD When 0 multi frame alignme...

Page 173: ...ier Note The value of these bits increments with each received trail trace identifier memory access when these bits are Fh a memory access will return them to 0h Register Name TT RSR Register Descript...

Page 174: ...Name Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name RTICIE RTIMIE RTIUIE RIDLIE Default 0 0 0 0 0 0 0 0 Bit 3 Receive Trail Trace Identifier Change Interrupt Enable RTICIE This bit enables an interr...

Page 175: ...ss will be incremented whenever these bits are read when byte Fh is read the address will return to 0h Register Name TT EIR Register Description Trail Trace Expected Identifier Register Register Addre...

Page 176: ...le Signal TIDLE 0 Transmit DS3 Idle signal is not inserted 1 Transmit DS3 Idle signal is inserted into the DS3 frame Bit 10 C bit Generation Disable CBGD M23 mode only When 0 Transmit Frame Processor...

Page 177: ...or Insertion Enable CCPEIE When 0 single C bit parity error insertion is enabled When 1 continuous C bit parity error insertion is enabled and C bit parity errors will be transmitted continuously if C...

Page 178: ...3 5 7 22h Reserved 1 3 5 7 24h T3 RSR1 T3 Receive Status Register 1 1 3 5 7 26h T3 RSR2 T3 Receive Status Register 2 1 3 5 7 28h T3 RSRL1 T3 Receive Status Register Latched 1 1 3 5 7 2Ah T3 RSRL2 T3 R...

Page 179: ...RAILE When 0 an LOF condition does not affect the receive alarm indication signal RAI When 1 an LOF condition will cause the transmit DS3 X bits to be set to zero if transmit automatic RDI is enabled...

Page 180: ...When 1 the receive frame processor is in an RUA1 condition Bit 7 Out Of Multi frame OOMF When 0 the receive frame processor is not in an out of multi frame OOMF condition When 1 the receive frame proc...

Page 181: ...0 Name OOMFL SEFL COFAL LOFL RAIL AISL OOFL LOSL Bit 11 T3 Framing Format Mismatch Latched T3FML This bit is set when the T3FM bit transitions from zero to one Bit 10 Application Identification Channe...

Page 182: ...PEL This bit is set when a P bit parity error is detected Bit 8 Framing Error Latched FEL This bit is set when a framing error is detected The type of framing error event that causes this bit to be se...

Page 183: ...Interrupt Enable RUA1IE This bit enables an interrupt if the RUA1L bit is set and the bit in GL ISRIE PSRIE 4 1 that corresponds to this port is set 0 interrupt disabled 1 interrupt enabled Bit 7 Out...

Page 184: ...IE PECIE FECIE Default 0 0 0 0 0 0 0 0 Bit 11 C bit Parity Error Interrupt Enable CPEIE This bit enables an interrupt if the CPEL bit is set and the bit in GL ISRIE PSRIE 4 1 that corresponds to this...

Page 185: ...ive Framing Error Count Register Register Address 1 3 5 7 34h Bit 15 14 13 12 11 10 9 8 Name FE15 FE14 FE13 FE12 FE11 FE10 FE9 FE8 Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name FE7 FE6 FE5 FE4 FE3...

Page 186: ...associated counter will not increment in M23 DS3 mode This register is updated via the PMU signal see Section 10 4 5 Register Name T3 RCPECR Register Description T3 Receive C bit Parity Error Count R...

Page 187: ...rry the same transmit FEAC controller one bit per frame period however the N bit and A bit in the same frame may or may not be equal Bits 3 to 2 Transmit A Bit Control TABC 1 0 These two bits control...

Page 188: ...sertion Enable FEI When 0 framing error insertion is disabled When 1 framing error insertion is enabled Bit 1 Transmit Single Error Insert TSEI This bit causes an error of the enabled type s to be ins...

Page 189: ...12 9 4 1 Register Bit Descriptions Register Name E3G751 RCR Register Description E3 G 751 Receive Control Register Register Address 1 3 5 7 20h Bit 15 14 13 12 11 10 9 8 Name Reserved Reserved DLS MD...

Page 190: ...on will cause the transmit E3 A bit to be set to one if transmit automatic RAI is enabled When 1 an OOF condition does not affect the RAI signal Bit 4 Receive Alarm Indication on AIS Disable RAIAD Whe...

Page 191: ...OF condition When 1 the receive frame processor is in an LOF condition Bit 3 Remote Alarm Indication RDI This bit indicates the current state of the remote alarm indication RDI Bit 2 Alarm Indication...

Page 192: ...fferent from the previous frame alignment Bit 4 Loss Of Frame Change Latched LOFL This bit is set when the LOF bit changes state Bit 3 Remote Alarm Indication Change Latched RDIL This bit is set when...

Page 193: ...gnment Interrupt Enable COFAIE This bit enables an interrupt if the COFAL bit and the bit in GL ISRIE PSRIE 4 1 that corresponds to this port are set 0 interrupt disabled 1 interrupt enabled Bit 4 Los...

Page 194: ...rrupt enabled Bit 0 Framing Error Count Interrupt Enable FECIE This bit enables an interrupt if the FECL bit is set and the bit in GL ISRIE PSRIE 4 1 that corresponds to this port is set 0 interrupt d...

Page 195: ...and NR byte will carry the same transmit HDLC controller eight bits per frame period however the GC byte and NR byte in the same frame may or may not be equal Bits 9 to 8 Transmit NR Byte Control TNRC...

Page 196: ...parity error is generated by inverting a single bit in the EM byte When 1 a parity error is generated by inverting all eight bits in the EM byte Bit 6 Continuous Parity Error Insertion Enable CPEIE Wh...

Page 197: ...from the four timing source indicator bits TTI 3 0 When 1 TTI 3 is ignored and TTI 2 0 are directly inserted into the last three bits of the MA byte Bits 3 to 0 Transmit Timing Source Indication TTI 3...

Page 198: ...5 7 3Ch Unused 1 3 5 7 3Eh Unused 12 9 6 1 Register Bit Descriptions Register Name E3G832 RCR Register Description E3 G 832 Receive Control Register Register Address 1 3 5 7 20h Bit 15 14 13 12 11 10...

Page 199: ...will cause the transmit E3 RDI bit to be set to one if transmit automatic RDI is enabled When 1 an AIS condition does not affect the RDI signal Bit 3 Receive Overhead Masking Disable ROMD When 0 the...

Page 200: ...ondition Bit 3 Remote Defect Indication RDI This bit indicates the current state of the remote defect indication RDI Bit 2 Alarm Indication Signal AIS When 0 the receive frame processor is not in an a...

Page 201: ...t that is different from the previous frame alignment Bit 4 Loss Of Frame Change Latched LOFL This bit is set when the LOF bit changes state Bit 3 Remote Defect Indication Change Latched RDIL This bit...

Page 202: ...oad Type Interrupt Enable RPTIE This bit enables an interrupt if the RPTL bit is set and the bit in GL ISRIE PSRIE 4 1 that corresponds to this port is set 0 interrupt disabled 1 interrupt enabled Bit...

Page 203: ...ISL bit is set and the bit in GL ISRIE PSRIE 4 1 that corresponds to this port is set 0 interrupt disabled 1 interrupt enabled Bit 1 Out Of Frame Interrupt Enable OOFIE This bit enables an interrupt i...

Page 204: ...0 interrupt disabled 1 interrupt enabled Bit 8 Framing Error Interrupt Enable FEIE This bit enables an interrupt if the FEL bit is set and the bit in GL ISRIE PSRIE 4 1 that corresponds to this port...

Page 205: ...e indicator bits extracted from the last three bits of the MA byte MA 6 8 When timing source indicator bit extraction is disabled TI 3 is zero and TI 2 0 contain the integrated version of the last thr...

Page 206: ...E14 PE13 PE12 PE11 PE10 PE9 PE8 Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Default 0 0 0 0 0 0 0 0 Bits 15 to 0 Parity Error Count PE 15 0 These sixteen bits indi...

Page 207: ...egister Bit Descriptions Register Name CC TCR Register Description Clear Channel Transmit Control Register Register Address 1 3 5 7 18h Bit 15 14 13 12 11 10 9 8 Name Reserved Reserved Reserved Reserv...

Page 208: ...7 36h Reserved 1 3 5 7 38h Reserved 1 3 5 7 3Ah Reserved 1 3 5 7 3Ch Unused 1 3 5 7 3Eh Unused 12 9 8 2 Register Bit Descriptions Register Name CC RCR Register Description Clear Channel Receive Contro...

Page 209: ...Reserved Reserved Reserved Reserved RUA1L Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved LOSL Default 0 0 0 0 0 0 0 0 Bit 8 Receive Un...

Page 210: ...troller Instruction Register Bypass Register Boundary Scan Register Device Identification Register The Test Access Port has the necessary interface pins namely JTCLK JTDI JTDO and JTMS and the optiona...

Page 211: ...ction Register is loaded with the IDCODE instruction All system logic and I O pads on the device operate normally This state can also be reached from any other state by holding JTMS high and clocking...

Page 212: ...g a rising edge on JTCLK puts the controller back into the Test Logic Reset state Capture IR The Capture IR state is used to load the shift register in the Instruction register with a fixed value of 0...

Page 213: ...he parallel outputs of all digital output pins are driven according to the values in the boundary scan registers on the positive edge of JTCLK The boundary scan register is connected between JTDI and...

Page 214: ...DE ID 27 12 MANUFACTURER S CODE ID 11 1 REQUIRED ID 0 DS3171 Consult factory 0000000001000100 00010100001 1 DS3172 Consult factory 0000000001000101 00010100001 1 DS3173 Consult factory 000000000100011...

Page 215: ...D VSS VSS VSS VSS VDD VDD VDD G VDD_JA1 A 3 A 7 JTDO GPIO 2 VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD H A 0 A 2 A 6 VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD J TXN1 TXP1 JTDI VDD_TX1 D 15 VSS VSS VSS VSS...

Page 216: ...H2 V GPIO 7 GPIO 8 D 10 TPOS2 TOHSOF 2 TOHCLK2 W VDD D 5 RNEG2 TCLKI2 TSOFI2 RLCLK2 Y VSS ROHSOF 2 RPOS2 TSOFO2 TLCLK2 VDD VSS Note Green indicates VSS red indicates VDD blank cells indicate No Connec...

Page 217: ...D VDD VSS VSS VSS VSS VDD VDD VDD H A 0 A 2 A 6 VDD VDD VDD VSS VSS VSS VSS VDD VDD VDD J TXN1 TXP1 JTDI VDD_TX1 D 15 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS K CLKA RDY RD WR VDD_CLA D VSS VSS VSS VSS...

Page 218: ...TION The package drawing s in this data sheet may not reflect the most current specifications The package number provided for each package is a link to the latest package outline information 15 1 400...

Page 219: ...ly connected to the internal GND plane of the PC board to achieve these thermal characteristics PARAMETER VALUE Target Ambient Temperature Range 40 C to 85 C Die Junction Temperature Range 40 to 125 C...

Page 220: ...ction tested Table 17 1 Recommended DC Operating Conditions VDD 3 3V 5 Tj 40 C to 85 C PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Logic 1 VIH 2 0 5 5 V Logic 0 VIL 0 3 0 8 V Supply VDD 5 VDD 3 135...

Page 221: ...mA TLCLKn O 6 TPOSn TDATn O 6 TNEGn O 6 TXPn O N A analog TXNn O N A analog TOHCLKn O 4 TOHSOFn O 4 ROHn O 4 ROHCLKn O 4 ROHSOFn O 4 TCLKOn TGCLKn O 6 TSOFOn TDENn O 6 RSERn O 6 RCLKOn RGCLKn O 6 RSO...

Page 222: ...1 Figure 18 2 Figure 18 3 and Figure 18 4 Definitions that are specific to a given interface are shown in that interface s subsection Figure 18 1 Clock Period and Duty Cycle Definitions Clock t1 t2 t2...

Page 223: ...Hold Setup and Delay Definitions Falling Clock Edge Clock Signal t5 t6 Signal t7 Figure 18 5 To From Hi Z Delay Definitions Rising Clock Edge Clock Signal t8 t9 Figure 18 6 To From Hi Z Delay Definit...

Page 224: ...Rn inputs Note 5 TCLKIn RLCLKn clock input to TSOFOn TDENn RSERn RSOFOn RDENn outputs Note 6 TCLKOn RCLKOn clock output to TSOFOn TDENn RSERn RSOFOn RDENn outputs 18 2 Line Interface AC Characteristic...

Page 225: ...uts 18 4 Overhead Port AC Characteristics All AC timing characteristics are specified with a 25 pF capacitive load on all output pins VIH 2 4V and VIL 0 8 The voltage threshold for all timing measurem...

Page 226: ...Width if not using RDY Handshake 35 ns 1 4 RD WR DS t9b Delay from RDY 15 ns 1 D 15 0 t10 Output Deassert Delay Time from RD DS Inactive 2 10 ns 1 3 CS R W t12 Hold Time from RD WR DS Inactive 0 ns 1...

Page 227: ...DS3171 DS3172 DS3173 DS3174 227 Figure 18 7 Micro Interface Nonmultiplexed Read Write Cycle D 15 0 RDY t8 t10 CS t6 t12 RD WR DS t9a A 10 0 t5 t1a D 15 0 t13 t14 t15 t16 t17 t18 t19 R W t20 t21 t9b...

Page 228: ...171 DS3172 DS3173 DS3174 228 Figure 18 8 Micro Interface Multiplexed Read Cycle D 15 0 RDY t8 t10 CS t6 t12 RD WR DS t9a D 15 0 t13 t14 t15 t16 t17 t18 t19 R W t20 t21 A 10 0 t1a ALE t2 t3 t4 t1b t9b...

Page 229: ...tions ANSI T1 102 and Bellcore GR 499 Table 18 7 DS3 Waveform Test Parameters and Limits PARAMETER SPECIFICATION Rate 44 736Mbps 20ppm Line Code B3ZS Transmission Medium Coaxial cable AT T 734A or equ...

Page 230: ...3 Transmission Medium Coaxial cable AT T 734A or equivalent Test Measurement Point At the transmitter Test Termination 75 1 resistive Pulse Amplitude 1 0V nominal Pulse Shape An isolated pulse precede...

Page 231: ...ITS Receive Sensitivity Length of Cable 900 1200 ft Signal to Noise Ratio Interfering Signal Test Notes 1 2 10 Input Pulse Amplitude RMON 0 Notes 2 3 1000 mVpk Input Pulse Amplitude RMON 1 Notes 2 3 2...

Page 232: ...for DS3 and unframed 2 23 1 PRBS for E3 Note 4 With respect to nominal 800mVpk signal for DS3 and nominal 1000mVpk signal for E3 Table 18 11 Transmitter Output Characteristics DS3 Modes VDD 3 3V 5 TA...

Page 233: ...5 ns JTMS and JTDI t5 Hold Time from JTCLK Rising Edge 10 ns JTMS and JTDI t6 Setup Time to JTCLK Rising Edge 10 ns JTDO t7 Delay from JTCLK Falling Edge 0 20 ns JTDO t8 Delay out of HiZ from JTCLK F...

Page 234: ...ated Products The Maxim logo is a registered trademark of Maxim Integrated Products Inc The Dallas logo is a registered trademark of Dallas Semiconductor 19 REVISION HISTORY DATE DESCRIPTION 102204 Ne...

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