MAX32660 User Guide
Maxim Integrated
Page 143 of 195
Because the controller does not start counting the high/low time until the input buffer detects the new value, the actual
clock behavior is based on many factors. These include bus loading, other devices on the bus holding SCL low, and the filter
delay time of this device.
12.13
SCL Clock Generation for Hs-Mode
In Hs-Mode, the I
2
C-bus specification requires a SCL clock HIGH to LOW ratio of 1 to 2,
𝑡
𝑆𝐶𝐿_𝐿𝑂
= 2 × 𝑡
𝑆𝐶𝐿_𝐻𝐼
. The
register is used for configuring the Hs-Mode clock high and low times. Calculate the number of peripheral
clocks for the Hs-Mode bit rate of 3.4 Mbps using
. Using the result,
pclk_count
, calculate the SCL high time
using
Equation 12-7: I
2
C High Speed Mode Clock Count
𝑝𝑐𝑙𝑘_𝑐𝑜𝑢𝑛𝑡 =
𝑓
𝑃𝐶𝐿𝐾
3,400,000
Equation 12-8: Hs-Mode SCL High Time Calculation
𝐼2𝐶𝑛_𝐻𝑆_𝐶𝐿𝐾. ℎ𝑠_𝑐𝑙𝑘_ℎ𝑖 =
𝑝𝑐𝑙𝑘_𝑐𝑜𝑢𝑛𝑡
3
− 1
Equation 12-9: Hs-Mode SCL Low Time Calculation
𝐼2𝐶𝑛_𝐻𝑆_𝐶𝐿𝐾. ℎ𝑠_𝑐𝑙𝑘_𝑙𝑜 =
(𝑝𝑐𝑙𝑘_𝑐𝑜𝑢𝑛𝑡 × 2)
3
− 1
Compensate for rounding errors in the calculation by rounding up the
hs_clk_hi
result if the least significant
bit is set.
12.14
TX FIFO Preloading
There may be situations where, when operating as a slave, firmware wants to preload the TX FIFO prior to a transmission,
such as when clock stretching is disabled. Firmware may also want to respond to an external master requesting data by
sending a NACK until the requested data is ready to transmit, rather than sending an ACK and then holding the bus low
while the data is prepared. By default, however, Address Match and General Call Match clear the TX FIFO preventing
firmware from preloading data into the TX FIFO. Firmware can change this behavior by enabling TX FIFO Preloading.
When TX FIFO Preloading is enabled, the application firmware controls ACKs to the external master using the TX Ready
(
txrdy
txrdy
is set to 0, hardware automatically NACKs all read transactions from
the Master. Setting
txrdy
to 1 sends an ACK to the Master on the next read transaction and transmits the
data in the TX FIFO. Preloading the TX FIFO must be complete prior to setting the
txrdy
field to 1.
