MaximIntegrated 16-5
MAX31782 User’s Guide
Revision 0; 8/11
Table16-3.InstructionRegister(IR[2:0])Encodings
When the parallel instruction register (IR2:0) is updated, the TAP controller decodes the instruction and performs any
necessary operations, including activation of the data shift register to be used for the particular instruction during data
register shift sequences (DR-Scan) . The length of the activated shift register depends upon the value loaded to the
instruction register (IR2:0) . The supported instruction register encodings and associated data register selections are
shown in
.
The Extest (IR[2:0] = 000b) and Sample/Preload (IR[2:0] = 001b) instructions are mandated by the JTAG standard; how-
ever, the MAX31782 does not intend to make practical use of these instructions . Hence, these instructions are treated
as no-operations but can be entered into the instruction register without affecting the on-chip system logic or pins and
do not change the existing serial data register selection between TDI and TDO .
The Bypass (IR[2:0] = 011b, 101b, or 111b) instruction is also mandated by the JTAG standard . The Bypass instruction
is fully implemented by the MAX31782 to provide a minimum length serial data path between the TDI and the TDO pins .
This is accomplished by providing a single-cell bypass shift register . When the instruction register is updated with the
Bypass instruction, a single bypass register bit is connected serially between TDI and TDO in the Shift-DR state . The
instruction register automatically defaults to the Bypass instruction when the TAP is in the Test-Logic-Reset state . The
Bypass instruction has no affect on the operation of the on-chip system logic .
The Debug (IR[2:0] = 010b) and System Programming (IR[2:0] = 100b) instructions are private instructions that are
intended solely for in-circuit debug and in-system programming operations, respectively . If the instruction register is
updated with the Debug instruction, a 10-bit serial shift register is formed between the TDI and TDO pins in the Shift-
DR state . If the System Programming instruction is entered into the instruction register (IR[2:0]), a 3-bit serial data shift
register is formed between the TDI and TDO pins in the Shift-DR state .
Instruction register (IR[2:0]) settings other than those listed and described are reserved for internal use . As shown in
, the instruction register serves to select the length of the serial data register between TDI and TDO during
the Shift-DR state .
16.2.4DR-ScanSequence
Once the instruction register has been configured to a desired state (mode), transactions are performed through a
data buffer register associated with that mode . These data transactions are executed serially in a manner analogous
to the process used to load the instruction register and are grouped in the TAP controller state sequence starting from
the Select-DR-Scan state . In the TAP controller state sequence, the Shift-DR state allows internal data to be shifted out
through the TDO pin while the external data is shifted in simultaneously through the TDI pin . Once a complete data pat-
tern is shifted in, input data can be latched into the parallel buffer of the selected register on the falling edge of TCK in
the Update-DR state . On the same TCK falling edge, in the Update-DR state, the internal parallel buffer is loaded to the
data shift register for output . This Shift-DR/Update-DR process serves as the basis for passing information between the
external host and the MAX31782 . These data register transactions occur in the data register portion of the TAP controller
state sequence diagram and have no affect on the instruction register .
IR[2:0]
INSTRUCTION
FUNCTION
SERIALDATASHIFTREGISTERSELECTION
000
Extest
No operation
Unchanged, retain previous selection
001
Sample/Preload
No operation
Unchanged, retain previous selection
010
Debug
In-circuit debug mode
10-bit shift register
011
Bypass
No operation (default)
1-bit shift register
100
System Programming
Bootstrap function
3-bit shift register
101
Bypass
No operation (default)
1-bit shift register
110
Reserved
Reserved
Reserved
111
Bypass
No operation (default)
1-bit shift register
