Burst Read
In this operation, the master sends an address plus two
data bytes and receives multiple data bytes from the slave
device (
). The following procedure describes the
burst byte read operation:
1)
The master sends a START condition
2) The master sends the 7-bit slave address plus a
write bit (low)
3) The addressed slave asserts an ACK on the data
line
4) The master sends the 8-bit register address
5) The slave asserts an ACK on the data line only if the
address is valid (NAK if not)
6) The master sends a REPEATED START condition
7) The master sends the 7-bit slave address plus a
read bit (high)
8) The slave asserts an ACK on the data line
9) The slave sends eight data bits
10)
The master asserts an ACK on the data line
11) Repeat 9 and 10 N-2 times
12)
The slave sends the last eight data bits
13)
The master asserts a NACK on the data line
14)
The master generates a STOP condition
Acknowledge Bits
Data transfers are acknowledged with an acknowledge bit
(ACK) or a not-acknowledge bit (NACK). Both the master
and the MAX20335 generate ACK bits. To generate an
ACK, pull SDA low before the rising edge of the ninth
clock pulse and hold it low during the high period of the
ninth clock pulse (see
). To generate a NACK,
leave SDA high before the rising edge of the ninth clock
pulse and leave it high for the duration of the ninth clock
pulse. Monitoring for NACK bits allows for detection of
unsuccessful data transfers.
Figure 10. Burst Read Sequence
Figure 11. Acknowledge
MAX20335
PMIC with Ultra-Low I
Q
Voltage Regulators and
Battery Chargers for Small Lithium Ion Systems
www.maximintegrated.com
Maxim Integrated
│
40
S
Sr
DEVICE SLAVE ADDRESS - W A
DEVICE SLAVE ADDRESS - R
BURST READ
A
REGISTER ADDRESS
A
8 DATA BITS - 1
A
A
8 DATA BITS - 3
8 DATA BITS - 2
A
8 DATA BITS - N
NA
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
P
NOT ACKNOWLEDGE
ACKNOWLEDGE
1
2
8
9
SDA
SCL
S