Matsushita Electric KX-TCD952NLB, Service Manual

Page: 14 / 62

The base-band section consists of a base-band integrated circuit (BBIC), a Flash PROM, an
EEPROM, and an AND Gate.
8.2.2. THE BASE-BAND INTEGRATED CIRCUIT (BBIC)
The PQVINSC14424 (IC101) is a CMOS device designed to handle all the audio, signal and data
processing needed in a DECT base unit. It contains a "burst mode controller” microprocessor
which takes care of DECT specific physical layer and radio section control. It also contains two
ADPCM transcoders, a low power 14 bit codec (ADC/DAC), various other ADC´s, DAC´s and
timers, a gaussian filter for the DECT GFSK modulation method, clock and data recovery
circuits, a clock oscillator circuit, a DTMF generator (DSP), an echo suppression circuit (DSP),
and a pair of gain controllable audio amplifiers for line input and line output and a general
purpose microcontroller. / The IC101 interfaces to its external PROM (IC102) via a data/address/
control bus. It connects to the EEPROM via a serial interface, and a second serial interface is
used during manufacture and service to connect to an external computer.
8.2.3. FLASH PROM (SEE Fig. 19)
The 1 Mbit (IC102) Flash PROM contains the operational firmware for the microcontroller. It is
interfaced to the data/address/control bus using address lines A0 to A16, data lines D0 to D7,
and chip select (pin 30), output enable (pin 32), and write (pin 7).
8.2.4. EEPROM (SEE Fig. 19)
The electrically erasable PROM PQVINM4C32L (IC103) is used to store all the temporary
operating parameters for the base (see EEPROM LAYOUT). It uses a two-line serial data
interface with the BBIC, with bi-directional data on pin 5 (TP94), and clock on pin 6 (TP93).
8.2.5. CLOCK GENERATION (SEE Fig. 19)
A single clock generator in the BBIC uses an external crystal X101 to derive all clock
frequencies used in the base. The crystal is tuned to the exact frequency of 10.368 MHz during
manufacture by feeding a DC voltage from a DAC in the microcontroller (from pin 14 of IC101) to
the varicap diode D104 (TP112). / The BBIC provide buffered clock signals RFCLK (pin 11,
TP139) at 10.368 MHZ for the Frequency Synthesizer, which is only active during the PLL lock
period. Other clock is SCLK on pin 1 (3.456MHz). The basic data rate for TRADAT and RECDAT
is 1.152 Mbits/s, which is 10.368 MHs divided by 9. The data rate for the serial interface to the
phase-lock-loop is also 1.152 Mbits/s.
Circuit Diagram
14